Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

code vhdl for multiplication matrix, need help

Status
Not open for further replies.
N

napiuuul

Newbie level 4
Joined
Nov 26, 2015
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
88
code vhdl for multiplication matrix .. need hekp

ccording this site

https://vhdlguru.blogspot.co.id/2010/03/matrix-multiplication-in-vhdl.html

i have tried but failed
i have followed every instruction but for matmu.vhd, the instruction not clear..
i created the file for matmul.vhd like this but what's wrong? the project couldn't be compiled

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
 
package matmul  is
 
type t11 is array (0 to numcols1-1) of unsigned(15 downto 0); 
type t1 is array (0 to numrows1-1) of t11;      
type t22 is array (0 to numcols2-1) of unsigned(15 downto 0);   
type t2 is array (0 to numrows2-1) of t22; 
type t33 is array (0 to numcols3-1) of unsigned(31 downto 0);   
type t3 is array (0 to numrows3-1) of t33;  
 
function  matmul  ( a : t1; b:t2 ) return t3 is
variable i,j,k : integer:=0;
variable prod : t3:=(others => (others => (others => '0')));
 
begin
for i in 0 to numrows1-1 loop
for j in 0 to numcols2-1 loop
for k in 0 to numcols1-1 loop
   prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j));
end loop;
end loop;
end loop;
return prod;
end matmul;
 
Last edited by a moderator:

Re: code vhdl for multiplication matrix .. need hekp

numcols, numrows are undefined.

also, this package was not intended for synthesis, although the blog post does not make that part clear.
 
Re: code vhdl for multiplication matrix .. need hekp

can you show me the right one please? actually i don't understand vhdl code well.. i'm a newbie.
Help :((
 

Re: code vhdl for multiplication matrix .. need hekp

napiuuul said:
can you show me the right one please? actually i don't understand vhdl code well.. i'm a newbie.
Help :((
Click to expand...

I suggest finding an online tutorial or finding a good vhdl textbook. There are plenty of recommendations if you use the search function or google...
 

Re: code vhdl for multiplication matrix .. need hekp

what's wrong with this ?

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package matmul is
type t11 is array (0 to 2) of unsigned(15 downto 0); 
type t1 is array (0 to 3) of t11;       
type t22 is array (0 to 4) of unsigned(15 downto 0); 
type t2 is array (0 to 2) of t22; 
type t33 is array (0 to 4) of unsigned(31 downto 0); 
type t3 is array (0 to 3) of t33;
end package;
 
package body matmul is
function  matmul  ( a : t1; b:t2 ) return t3 is
variable i,j,k : integer:=0;
variable prod : t3:=(others => (others => (others => '0')));
 
begin
for i in 0 to numrows1-1 loop
for j in 0 to numcols2-1 loop
for k in 0 to numcols1-1 loop
   prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j));
end loop;
end loop;
end loop;
return prod;
end matmul;
end package body;


error : Error (10289): VHDL Subprogram Specification error at matmul.vhd(14): subprogram "matmul" is a homograph of another object in the same declarative region
 
Last edited by a moderator:

Re: code vhdl for multiplication matrix .. need hekp

napiuuul said:
what's wrong with this ?

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
package matmul is
type t11 is array (0 to 2) of unsigned(15 downto 0);
type t1 is array (0 to 3) of t11;
type t22 is array (0 to 4) of unsigned(15 downto 0);
type t2 is array (0 to 2) of t22;
type t33 is array (0 to 4) of unsigned(31 downto 0);
type t3 is array (0 to 3) of t33;
end package;

package body matmul is
function matmul ( a : t1; b:t2 ) return t3 is
variable i,j,k : integer:=0;
variable prod : t3:=(others => (others => (others => '0')));

begin
for i in 0 to numrows1-1 loop
for j in 0 to numcols2-1 loop
for k in 0 to numcols1-1 loop
prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j));
end loop;
end loop;
end loop;
return prod;
end matmul;
end package body;

error : Error (10289): VHDL Subprogram Specification error at matmul.vhd(14): subprogram "matmul" is a homograph of another object in the same declarative region
Click to expand...

Apparently you can't name the package "matmul" and the function "matmul". You can name the package something else, perhaps matrix_pkg.
 
Re: code vhdl for multiplication matrix .. need hekp

how about this?

Code VHDL - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189

behavioral file:
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
entity DCT_beh is
    port (
            Clk :           in std_logic;
            Start :         in std_logic;
            Din :           in INTEGER;
            Done :          out std_logic;
            Dout :          out INTEGER
          );
 end DCT_beh;
 
architecture behavioral of DCT_beh is 
begin
    process
            type RF is array ( 0 to 7, 0 to 7 ) of INTEGER;
 
            variable i, j, k        : INTEGER;
            variable InBlock        : RF;
            variable COSBlock       : RF;
            variable TempBlock      : RF;
            variable OutBlock       : RF;
            variable A, B, P, Sum   : INTEGER; 
 
    begin
 
            COSBlock := ( 
    ( 125,  122,    115,    103,    88,     69,     47,     24  ),
    ( 125,  103,    47,     -24,    -88,    -122,   -115,   -69  ),
    ( 125,  69,     -47,    -122,   -88,    24,     115,    103  ),
    ( 125,  24,     -115,   -69,    88,     103,    -47,    -122  ),
    ( 125,  -24,    -115,   69,     88,     -103,   -47,    122  ),
    ( 125,  -69,    -47,    122,    -88,    -24,    115,    -103  ),
    ( 125,  -103,   47,     24,     -88,    122,    -115,   69  ),
    ( 125,  -122,   115,    -103,   88,     -69,    47,     -24  )
                    );
 
--Starting
    wait until Start = '1';
        Done <= '0';
 
--Read Input Data
    for i in 0 to 7 loop
        for j in 0 to 7 loop    
            wait until Clk = '1' and clk'event;
            InBlock(i,j) := Din;
        end loop;
    end loop;
 
--TempBlock = COSBLOCK * InBlock 
 
    for i in 0 to 7 loop
        for j in 0 to 7 loop
            Sum := 0;
            for k in 0 to 7 loop
                A := COSBlock( i, k ); 
                B := InBlock( k, j ); 
                P := A * B; 
                Sum := Sum + P; 
                if( k = 7 ) then 
                TempBlock( i, j ) := Sum;
                end if;
            end loop;
        end loop;
    end loop;
 
 
--Finishing 
 
    wait until Clk = '1' and Clk'event;
    Done <= '1';
 
--Output Data
 
    for i in 0 to 7 loop
        for j in 0 to 7 loop
            wait until Clk = '1' and Clk'event;
            Done <= '0';
            Dout <=  tempblock(i,j);
        end loop;
    end loop;
end process;      
 end behaviorall;
 
testbench file:
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
 ENTITY lab4b_tb IS
 END lab4b_tb;
 
ARCHITECTURE behavior OF lab4b_tb IS 
 
-- Component Declaration for the Unit Under Test (UUT)
 
COMPONENT DCT_beh
PORT(
     Clk : IN  std_logic;
     Start : IN  std_logic;
     Din : IN  INTEGER;
     Done : OUT  std_logic;
     Dout : OUT  INTEGER
    );
END COMPONENT;
 
 
   --Inputs
   signal Clk : std_logic := '0';
   signal Start : std_logic := '0';
   signal Din : INTEGER;
 
--Outputs
   signal Done : std_logic;
   signal Dout : INTEGER;
 
   -- Clock period definitions
   constant Clk_period : time := 10 ns;
 
 BEGIN
 
-- Instantiate the Unit Under Test (UUT)
   uut: DCT_beh PORT MAP (
      Clk => Clk,
      Start => Start,
      Din => Din,
      Done => Done,
      Dout => Dout
    );
 
   -- Clock process definitions
   Clk_process :process
   begin
    Clk <= '0';
    wait for Clk_period/2;
    Clk <= '1';
    wait for Clk_period/2;
  end process;
 
 
  -- Stimulus process
  stim_proc: process
 
variable i, j : INTEGER;
variable cnt : INTEGER;
 
  begin     
     -- hold reset state for 100 ns.
 
     wait for 100 ns;   
 
        start <= '1'; 
        wait for clk_period; 
        start <= '0';
 
    for cnt in 0 to 63 loop
        wait until clk = '1' and clk'event;
            din <= cnt;
        end loop;
 
        --wait for 100 ns;
 
        --start <= '1';
        --wait for clk_period;
        --start <= '0';
 
        --for i in 0 to 63 loop
          -- wait for clk_period;
            --if (i < 24) then
                --din <= 255;
            --elsif (i > 40) then
                --din <= 255;
            --else
                --din <= 0;
            --end if;
        --end loop;
 
 
  wait;
  end process;
 
END;


the errors are
Error (10398): VHDL Process Statement error at DCT_beh.vhd(46): Process Statement must contain only one Wait Statement
Error: Can't elaborate top-level user hierarchy

need help
 
Last edited by a moderator:

Re: code vhdl for multiplication matrix .. need hekp

Id say the error was fairly obvious wasnt it? Process statements must constain only one wait statement.

The problem though is that the VHDL is written like some software. VHDL is NOT a programming language, it is a hardware description language. I suggest you start your VHDL again, but before then draw the circuit your are trying to describe on a peice of paper. As a description language, it requires you to understand the circuit you are trying to create before you actually write the code. You need to do this by following the templates for specific design elements, which should be explained in any good vhdl tutorial.
 

Re: code vhdl for multiplication matrix .. need hekp

Architecturally your "software" will result in a design that synthesizes to a huge number of flip-flops that may be difficult to implement in an FPGA as your design is inefficient. Usually things like matrix operations on larger matrices is done by storing the matrix in RAM and having an FSM sequence though the matrix operation, generating the correct addresses to the RAM to perform the calculation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top