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ADC Verilog Code for Spartan 3E Starter Kit

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prakhars

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I am working with Spartan 3E Starter kit and I need to use onboard ADC.
I have written many codes but they are not working as intended.
If possible kindly share ADC driver code in verilog.

Thanks in Advance :)
 

Instead of just asking someone to do your homework for you, why not post the code you're having problems with so that we can help to get it working.

1. Have you written a testbench and simulated your code?
 

This is one of the simplest code I wrote
In this Code I've reduced clock to 10MHz frequency, and then used it on the board for easy verification...
I've tied VINA to VCC and to GND but getting nothing on the LEDs.

Code Verilog - [expand]
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`timescale 1ns / 1ps
module ADC_N(
    input CLK,
//Pre Amplifier Interface
     output reg SPI_MOSI,
     output reg AMP_CS,
     output SPI_SCK,
     output AMP_SHDN,
     //input AMP_DOUT,
// The ADC interface
     output  reg AD_CONV,
     input SPI_MISO,
// Output to LEDs
     output reg  [7:0]LED
     //output LED
    );
     
wire OPCLK;
reg [7:0]SUB_LED;
reg [7:0]GAIN_AB='b00110011;
reg [7:0]COUNTER=0;
reg STOP_CLK=0;
reg [13:0]ADC_A,ADC_B;
CLOCK C1(CLK,OPCLK);
assign AMP_SHDN=0;
assign SPI_SCK=STOP_CLK?0:OPCLK;
//assign LED=ADC_A[7:0];
//assign LED=COUNTER[7:0];
//assign LED=SPI_MISO;
always@(posedge OPCLK)
begin
    case(COUNTER)
        1: AMP_CS=0;
        2: SPI_MOSI=GAIN_AB[7];
        3: SPI_MOSI=GAIN_AB[6];
        4: SPI_MOSI=GAIN_AB[5];
        5: SPI_MOSI=GAIN_AB[4];
        6: SPI_MOSI=GAIN_AB[3];
        7: SPI_MOSI=GAIN_AB[2];
        8: SPI_MOSI=GAIN_AB[1];
        9: SPI_MOSI=GAIN_AB[0];
        11: STOP_CLK=1;                         // Clock is stopped
        
        20:AD_CONV=1;
        22:AD_CONV=0;
        25:begin 
                STOP_CLK=0;                         // Clock is allowed to pass
            end
        
    endcase
    COUNTER=COUNTER+1;
    if(COUNTER==59)
        COUNTER=10;
end
 
always@(negedge OPCLK)
begin
    if(COUNTER>25)
    begin
        case(COUNTER)
        26: ADC_A[13]=SPI_MISO;
        27: ADC_A[12]=SPI_MISO;
        28: ADC_A[11]=SPI_MISO;
        29: ADC_A[10]=SPI_MISO;
        30: ADC_A[9]=SPI_MISO;
        31: ADC_A[8]=SPI_MISO;
        32: ADC_A[7]=SPI_MISO;
        33: ADC_A[6]=SPI_MISO;
        34: ADC_A[5]=SPI_MISO;
        35: ADC_A[4]=SPI_MISO;
        36: ADC_A[3]=SPI_MISO;
        37: ADC_A[2]=SPI_MISO;
        38: ADC_A[1]=SPI_MISO;
        39: begin ADC_A[0]=SPI_MISO;
                    LED=ADC_A[7:0];
                    end
        42: ADC_B[13]=SPI_MISO;
        43: ADC_B[12]=SPI_MISO;
        44: ADC_B[11]=SPI_MISO;
        45: ADC_B[10]=SPI_MISO;
        46: ADC_B[9]=SPI_MISO;
        47: ADC_B[8]=SPI_MISO;
        48: ADC_B[7]=SPI_MISO;
        49: ADC_B[6]=SPI_MISO;
        50: ADC_B[5]=SPI_MISO;
        51: ADC_B[4]=SPI_MISO;
        52: ADC_B[3]=SPI_MISO;
        53: ADC_B[2]=SPI_MISO;
        54: ADC_B[1]=SPI_MISO;
        55: ADC_B[0]=SPI_MISO;
        endcase
    end
end
endmodule
 
 
module CLOCK(
    input CLK,
    output reg OPCLK=0
    );
reg [28:0]COUNTER=0;
 
always@(CLK)
begin
    if(COUNTER==5)
    begin
        OPCLK=~OPCLK;
        COUNTER=0;
    end
    COUNTER=COUNTER+1;
end
 
endmodule

- - - Updated - - -

Yes I am using this manual UG230.pdf
 
Last edited by a moderator:

prakhars said:
and then used it on the board for easy verification...
Click to expand...

This is an oxymoron - Trying to do verfication on a board is not easy and will chew through lots of time.
It sounds like you need to build a testbench to check the behaviour of your code.

And another point - do not use logic generated clocks. you should create clock enables instead as this will not cause timing issues you get with logic clocks.
 

Can anybody provide me timing diagram of Spartan 3e board's ADC Timing Diagram other than mentioned in ug230.pdf manual.
 

prakhars said:
Can anybody provide me timing diagram of Spartan 3e board's ADC Timing Diagram other than mentioned in ug230.pdf manual.
Click to expand...
Oh, boy did you read UG230? The part used on the board is called out on page 81. If you click on the link provide on page 81 it takes you to the following PDF datasheet?

Using a brute force approach with large mulitplexers for something that should be done with shift registers is probably part of your problem, besides the lack of a testbench and simulation.
 
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