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Reading byte by byte from a register

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Hi,
I have 128 bit (i.e. 16 byte) single register and I would like to read from it byte by byte.
How I can do that in verilog?

Is this approach ok?
Code Verilog - [expand]
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reg [127:0] source_reg;
reg [7:0] target_reg;
reg [3:0] i = 0;
always @ (posedge clk)
begin
     for (i=0; i<15; i=i+1)
       begin
           target_reg <= source_reg[8*i +:8]; //target_reg is intended to be written in a 8 bit fifo.
           write_fifo <= 1;
       end
end
 

I notice that this isn't the very first FPGA code you are dealing with, although one could suspect at first sight.

So you can you refer to things you have learned before.

A for loop doesn't constitute a sequence in time, instead it goes through all iteration steps at once, in a single clock cycle. Your code ends up with writing the last target_reg value to the FIFO, skipping all previous ones.

To write all bytes one by one you have to design a state machine.
 
If target_reg has to be written to a FIFO then you can do only a single write every cycle which means a single read of 8 bits every cycle. You will not need the for loop in that case.
You will run a counter for 16 cycles and then write a case statement (using this counter) to index source_reg and assign it to target_reg.
 
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