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[SOLVED] [moved] Can't get data from I2C slave register with FPGA

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Yes right but in FPGA there is no I2C you have to develop it using hardware programming, that why all this we have to consider in software.

Huh? What does this have to do with software!?

You can emulate open-drain/open-collector on an FPGA, so what are you trying to say?
 

It should be high when no data transfer.

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First of all your hardware configuration should be like this.


After that check with timing diagram.

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Huh? What does this have to do with software!?

You can emulate open-drain/open-collector on an FPGA, so what are you trying to say?

Right boss :cool:
 

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My hardware description is true. On evaluation kit this circuit have already presented.

I removed ACK state (STATE_ACK3) after when I2C address sent, and I got more reasonable result.
Circuit gets ACK wait DATA transfer. I try to read green low byte from address 0x98, repeated start and read state scope out as below.
But data byte read as 00000000, It must be more than it. I wonder if repeated start condition is wrong. However I get ACK after data byte.

DSC_0442.jpg

I turn the all of HIGH valued SDA and SCL to HIGH-Z, otherwise FPGA can't get any response from light sensor.
 

I would prefer a waveform with a start condition after an idle period along with a description what's intended to do in each stage and which part you suspect to be wrong.
 

I suspect state repeated start and ack state after i2c address reading. I send register enable on before read state and gets ack but still data line seems low.

My general algorihm like that, firstly write data to enable register then reading data.

START -> I2C ADDRESS + 0 -> ACK -> REGISTER ENABLE ADDRESS (0x80) -> ACK -> WRITED DATA (0x03) -> ACK -> STOP

START -> I2C ADDRESS + 0 -> ACK -> DATA REGISTER ADDRESS -> ACK -> I2C ADDRESS + 1 -> ACK -> DATA READ -> ACK -> STOP
 

Now I can get data from device, than you for your explanations and suggestions.

dataoutput.png
 

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