Gated Clock in Altera

ivlsi · Nov 24, 2015

Hi All,

How should I implement a Gated Clock in Altera devices? Is there some specific cell, which I should use?

Thank you

FvM · Nov 24, 2015

Depending on the used FPGA family, a CLKCTRL block might do what you want. It's rather unusual to have gated clocks in FPGA designs.

TrickyDicky · Nov 24, 2015

Why do you want one? whats wrong with a normal clock?

ads-ee · Nov 24, 2015

And why doesn't using a clock enable work? If you are trying to save power then using an FPGA is the primary problem.