Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Constraning an asynchronous design

Status
Not open for further replies.
Sure.
Yet the only signal that requires CDC attention is the SCLK that's arriving to the slave. I.E, although this bus isn't synchronous to the FPGA system clock - it still has properties inherent to the protocol that we can exploit.
 

If you can ignore all previous advice, then yes, all previous advice is what you wanted to hear.
 

shaiko said:
BTW,
ads-ee

About the double synchronizer you mentioned in post #2.

With a lower SCLK frequency - for example: 10MHz instead of the nominal 40MHz.
The only signal that will require double sampling is the SCLK on FPGA #2.
Neither MOSI (incoming towards FPGA #2) nor MISO (incoming towards FPGA #1) require double sampling. By protocol definition they're stable when we require their value (falling egde of SCLK).
Click to expand...

I would double sample, because in one word I'm "paranoid".

Basically I don't trust anyone else's designs, because I'm the one they always call in to fix someone else's F*** *P. That usually means both ends are suspect. Like the time I found a problem with the design I was called in to fix where the transmit side was tri-stating the output of the data intermittently a half clock cycle early, synchronous with the capture edge of the clock on an interface like SPI that has 180 phase shift between clock and data.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top