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can clk multiplleing be done by DCM?

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milan.km said:
thanks ,will u explain it more?
i am new to the design and i would appreciate if u explain how did u get 26.2144 MHz?
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256x256x25x16=26214400

and ~26 MHz is very easy in an FPGA even a Spartan 6, which can easily handle designs running at 200MHz. So running the entire design at the output pixel clock rate is probably the simplest way to implement this design. Just use clock enables in your code to operate some portions of the design at the lower clock rates. You probably won't even need to add multicycle constraints as 26 MHz should still be easy to meet timing with.
 

but the minimum freq for real time image processing is 50 MHZ.and my design still has some problems
 

milan.km said:
but the minimum freq for real time image processing is 50 MHZ.and my design still has some problems
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If you can't meet timing in a S6 at 50 MHz then you didn't pipeline your design properly or think about the levels of 6-input LUT usage required to implement some piece of logic.
 

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