xiaoanime
Newbie level 2
Hi, i am trying to convert verilog code to vhdl, however i have some problem face at this part. Would like to double check it if i convert it correctly.
Code Verilog - [expand] 1 2 3 4 5 6 assign oREAD_SDRAM_EN = ((x_cnt>Hsync_Blank-2)&& //214 (x_cnt<(H_LINE-Hsync_Front_Porch-1))&& //1015 (y_cnt>(Vertical_Back_Porch-1))&& // //34 (y_cnt<(V_LINE - Vertical_Front_Porch)) //515 )? 1'b1 : 1'b0;
Code VHDL - [expand] 1 2 3 4 5 6 7 oread_sdram_en <= '1' when x_cnt > Hsync_Blank - 2 and -- 214 x_cnt < H_LINE - Hsync_Front_Porch - 1 and -- 1015 y_cnt > Vertical_Back_Porch - 1 and -- 34 y_cnt < V_LINE - Vertical_Front_Porch else -- 515 '0';
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