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conversion from verilog to vhdl

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xiaoanime

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Hi, i am trying to convert verilog code to vhdl, however i have some problem face at this part. Would like to double check it if i convert it correctly.

Code Verilog - [expand]
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assign  oREAD_SDRAM_EN 
= ((x_cnt>Hsync_Blank-2)&& //214
(x_cnt<(H_LINE-Hsync_Front_Porch-1))&& //1015
(y_cnt>(Vertical_Back_Porch-1))&& // //34
(y_cnt<(V_LINE - Vertical_Front_Porch)) //515
 )?  1'b1 : 1'b0;


Code VHDL - [expand]
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oread_sdram_en <= '1' 
when x_cnt > Hsync_Blank - 2  and  -- 214
                           x_cnt < H_LINE - Hsync_Front_Porch - 1 and -- 1015
                           y_cnt > Vertical_Back_Porch - 1 and  -- 34
                           y_cnt < V_LINE - Vertical_Front_Porch
 else -- 515
                  '0';
 
Last edited by a moderator:

I would love to avoid this much big combinatorial logic in the 1st place.
but still if you want to write this code in HDL just for simulation purpose then, what problems you are facing ?
can you post the whole code, or post the errors if any ?
 

based on the commented numbers and assuming the right side of the compares are constants...

You've got 20 inputs to that combinational circuit. Even if you are using a 6-input LUT it will probably take 4 LUTs to do this with at least 2 levels. Not terrible, but certainly not the best way to generate an enable to a RAM. I would pipeline this operation and use a registered output to generate the enable to the RAM. Of course this might not be necessary if you are using a fast part and your clock frequency is low and you can afford the RAM being enabled randomly from glitches being produced by the combinational logic.
 

@op:
do you have the correct types for the signals. It looks like they aren't std_logic_vector as you use "+" and "-". (or you imported std_logic_unsigned).
 

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