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DCERPC Packet during UDP transmission in FPGA

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DCERPC Packet during UDP transmission from FPGA

Hi Everybody,

I am sending UDP packet from FPGA to PC and observing it on wireshark. I received correct UDP packet but wireshark also shows DCERPC Packet send from FPGA to PC which I have not sent.
What is it?
Is there anyway to filter it?

Best Regards
 

If you have the UDP packet on port 135 wireshark may think the packet is for DCERPC (Distributed Computing Environment/Remote Procedure Call)
 
Hi,

But I am sending to different port (5001 for receiving and 6001 for sending) and not 135 port.

Is there not any way to filter it?

Or is it not really sending from FPGA just wireshark setting problem?
 

Based on the page I found the previous description of the protocol, Wireshark doesn't seem to have a way to filter them out.

Do you know what the packet you are sending looks like (on the FPGA side), like capturing the data sent to the PHY? Perhaps the packet is getting malformed when being sent, resulting in the problem.
 

I don't exactly understand the description. Are you seeing two packets or one per UDP transmission? If you see two, I expect there's actually a different communication (attempt) going on. You can either analyze what it is or filter it out.
 

Do you know what the packet you are sending looks like (on the FPGA side), like capturing the data sent to the PHY? Perhaps the packet is getting malformed when being sent, resulting in the problem.
I have 10 bit ADC data which I am sending via Ethernet after some processing. I also receive correct packet.

- - - Updated - - -

I don't exactly understand the description. Are you seeing two packets or one per UDP transmission?
I give some commands to Fpga, based on that it sends ADC data after some processing in certain interval. and I receive correct data along with one DCERPC packet in each receive. DCERPC doesn't appear in wireshark when I want to have small size of data(let's say <2000 byte).
 

So is the FPGA Ethernet using a microblaze or just HDL code to perform the encapsulation of the ADC data? If it's the former then the code on the microblaze is probably doing something you obviously don't want. If you wrote the HDL code to UDP encapsulate the ADC data then you must be sending the DCERPC frames.

That's why I asked if you verified using chipscope/vivado debug cores to see what is sent to the PHY and verify that it's only the UDP frames.

Are there any other devices between the FPGA and the PC Ethernet connections? Perhaps one of them is inserting this extra DCERPC frame.
 
Hi,
I am using Niosii processor from Altera which set the parameters like packet size, ip/udp address, port etc. but HDL code is used to encapsulate ADC data in udp frame.

I am using Altera Fpga so I don't have chance to use chipscope/Vivaldo.

No there is no other device between PC and Fpga.
 

Well Altera the equivalent is Signaltap, which you can use.

But given you are doing the encapsulation of the ADC data in HDL code and not the Nios-II, means that the problem is probably on the receive side of the connection (the PC), that's assuming you've simulated your HDL code and know it only produces the correct UDP packets for all settings especially those that are jumbo frames i.e. greater than the 1500 bytes of payload. Or maybe that is your problem you are producing bad packets that aren't jumbo frames?

Have you tried a different PC with wireshark? Perhaps the PC you are using has a virus or something on it. From what I've read it appears that the DCERPC protocol is a target for exploits, it's had a number of issues on windows platforms.
 
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