sandik93
Newbie level 3
Hello,
I created a schematic file to make a FIFO buffer and added 2 modules(mux and UC code written in verilog symbols created and added to the main schematic) and made a verilog test fixture for it. After running simulation behavioral model appeared 11 errors of the same type:
ERROR:HDLCompiler:25 - "D:/.../fifo_buffer/main.vf" Line 562: Module <UC_MUSER_main> does not have a port
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
Any help would be really appreciated.
I created a schematic file to make a FIFO buffer and added 2 modules(mux and UC code written in verilog symbols created and added to the main schematic) and made a verilog test fixture for it. After running simulation behavioral model appeared 11 errors of the same type:
ERROR:HDLCompiler:25 - "D:/.../fifo_buffer/main.vf" Line 562: Module <UC_MUSER_main> does not have a port
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
Any help would be really appreciated.
