VHDL Time Delay Problem?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity main is
port (
		clk : in STD_LOGIC;
		onoff : in STD_LOGIC;
		DQ : inout STD_LOGIC;
		led_test : out STD_LOGIC);

end main;



architecture Behavioral of main is



signal DQ_in: STD_LOGIC;
signal dev_present: STD_LOGIC; -- 1 if device answers.
signal new_clk: STD_LOGIC:='0'; -- 2us clock
signal onoff_in: STD_LOGIC:='0'; -- 2us clock

begin

onoff_in <=onoff;

clk_proc: process (clk)

variable clk_cnt: integer:=0; 

begin

if rising_edge(clk) then --Mclk 20ns
clk_cnt := clk_cnt+1;
	
	if (clk_cnt = 100) then
	clk_cnt := 0;
	new_clk <= not new_clk;--2 us clk
	end if;
	
end if;
end process;



-- 1wire bus pulled low for min 480us by master => "reset"
p1: process(new_clk,onoff_in)  

variable loop_cnt: integer:=0; 

begin
if (onoff_in = '1') then

--wait 1ms
while (loop_cnt < 501) loop
	if rising_edge(new_clk) then
	loop_cnt:= loop_cnt + 1;
	end if;
end loop;
loop_cnt:=0; --reset counter


DQ <= '0'; --pull bus low


--wait 500us
while (loop_cnt < 251) loop
	if rising_edge(new_clk) then
	loop_cnt:= loop_cnt + 1;
	end if;
end loop;
loop_cnt:=0; --reset counter


DQ <='Z';-- pullup resistor restores DQ bus to high



-- slave detects bus rising to pullup waits 15 to 60us then pulls bus low for 60 to 240us => "present"
  
--wait 90us for slave 

while (loop_cnt < 46) loop
	if rising_edge(new_clk) then
	loop_cnt:= loop_cnt + 1;
	end if;
end loop;
loop_cnt:=0; --reset counter

end if;
end process;

DQ_in <=DQ;                 --sample DQ
dev_present<= not DQ_in;



led_test<=dev_present;


end Behavioral;

DQ <= out_val when (dq_enable = '1') else 'Z';

p1 : process (new_clk) is
begin
  if rising_edge(new_clk) then
    if onoff = '1' then -- this seems to be a clock enable
      cnt <= cnt + 1; -- default
      case (state) is
      when WAIT_1MS =>
        if cnt >= CNT_1MS then -- might be off by 1 if not careful
          cnt <= 0; -- reset count for next wait
          DQ <= '0'; -- this might need to be broken up to DQ_oe and DQ_val
        end if;
      -- add other states here
      end case;
    end if;
  end if;
end process;

DQ_pin <= DQ when (DQ = '0') else 'Z';