Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Synthesis : who we finalize synthesis, which report should we check and clean?

Status
Not open for further replies.

mepriyasingh

Member level 2
Joined
Sep 20, 2015
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
255
how we finalize synthesis, which report should we check and which should be clean in what sence.
 

After synthesis, you can check:
- Clock ideal STA. Knowing critical parts about timing in you design functional mode.
- Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them.
- SDC quality. ( report by check timing and so on .. )

If you want, you can check power report, but it is not closed to final number because lacking of clock cells and optimization cells.
 

After synthesis, you can check:
- Clock ideal STA. Knowing critical parts about timing in you design functional mode.
- Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them.
- SDC quality. ( report by check timing and so on .. )

If you want, you can check power report, but it is not closed to final number because lacking of clock cells and optimization cells.

Actully I want know that how we can say after see which which reports, say i have done synthesis and this netlist, we can deliver to rest of the team like PD, or for LEC team
 

There is no report says "OK to release". You need to clarify what is your target of synthesis.
Basically, synthesis need to clean "0" clock latency timing and Formal verification. The rest of thing like cell counts, static power ... are not so important as this phase, but it is depended on your targets before doing synthesis.
 

There is no report says "OK to release". You need to clarify what is your target of synthesis.
Basically, synthesis need to clean "0" clock latency timing and Formal verification. The rest of thing like cell counts, static power ... are not so important as this phase, but it is depended on your targets before doing synthesis.

In general what will be the aspect to finalize.
 

- Timing
- Formal verification
- Cell counts
- Area
- Static power ( Optional )
- FF count ( Info )
 

In General, if TIMING is MET for your targeted frequency, you are good to start with PnR. But you should also check the above points posted by "slutarius" and make sure you are OK with Area; FF count; Power; etc.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top