whack
Member level 5
I am implementing address translation for old nibble-mode DRAM input signals. This DRAM receives address in two halves, MSB half on falling edge of /RAS and then the LSB half on /CAS falling edge. After /CAS going down the first time DRAM outputs data. /CAS will go down three more times (for a total of four times) to get consecutive data out, but now DRAM chip shall ignore the address bus and increment the address in register/latch. This is called "nibble-mode" because the chip receives the address once but outputs four times in series.
The edge events are in order as follows /RAS, /CAS, /CAS, /CAS, /CAS, <don't care>, /RAS, /CAS, /CAS, /CAS, /CAS, <don't care>, etc...
Inside <don't care> there could be /CAS edge events, they are either DRAM refresh (CAS-before-RAS), those need to be ignored!
Timing diagram in datasheet:
https://www.jameco.com/Jameco/Products/ProdDS/41398TI.pdf
Note: we can't use page mode, only nibble-mode!!!
The destination memory is PSRAM on my FPGA board. The FPGA is a Spartan3E. PSRAM has a 23-bit parallel address bus, no halves here.
If you are confused now, we are taking nibble-mode DRAM control signals as input, and translating them into signals for PSRAM.
The following snippet of Verilog code is the FSM for getting full address (18-bit) and incrementing it for nibble-mode output. The "shift" bus is the I/O bus of my FPGA board. "Adr" register stores the full address.
However when I try to synthesize it, I get the following errors:
Thanks in advance!
PS the hardware design I can't change. It's an old machine with nibble-mode DRAM interface.
The edge events are in order as follows /RAS, /CAS, /CAS, /CAS, /CAS, <don't care>, /RAS, /CAS, /CAS, /CAS, /CAS, <don't care>, etc...
Inside <don't care> there could be /CAS edge events, they are either DRAM refresh (CAS-before-RAS), those need to be ignored!
Timing diagram in datasheet:
https://www.jameco.com/Jameco/Products/ProdDS/41398TI.pdf
Note: we can't use page mode, only nibble-mode!!!
The destination memory is PSRAM on my FPGA board. The FPGA is a Spartan3E. PSRAM has a 23-bit parallel address bus, no halves here.
If you are confused now, we are taking nibble-mode DRAM control signals as input, and translating them into signals for PSRAM.
The following snippet of Verilog code is the FSM for getting full address (18-bit) and incrementing it for nibble-mode output. The "shift" bus is the I/O bus of my FPGA board. "Adr" register stores the full address.
Code:
always @(negedge RAS, negedge CAS) begin
case(state)
0: begin
if (~RAS & CAS) begin
Adr[8:0] = shift[25:17];
state <= 1;
end
end
1: begin
if (~CAS) begin
Adr[17:9] = shift[25:17];
state <= 2;
end
end
2: begin
if (~CAS) begin
Adr = Adr+1;
state <= 3;
end
end
3: begin
if (~CAS) begin
Adr = Adr+1;
state <= 4;
end
end
4: begin
if (~CAS) begin
Adr = Adr+1;
state <= 0;
end
end
endcase
endI'm not sure what it's not liking about these registers (they are not driven anywhere else), and better yet, how to rewrite this to make it synthesizable?
Thanks in advance!
PS the hardware design I can't change. It's an old machine with nibble-mode DRAM interface.
