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Using 2 clock inputs in a FPGA

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djnik1362

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Hi

I have a design that using a clock for driving an audio CODEC and audio processing stuffs at 18.432 MHz and a 50 MHz clock for other
stuffs . Can i use these Non-Synchronized clocks with each other in a same design ? I prefer to use a DCM with 18.432 MHz input but the best frequency i can get is 50.688 MHz .

Whats is the best solution for this scheme ?

Thanks for your support .
 

I'm not 100% certain on your requirements but usually the way to do it is using a PLL to generate clocks. And luckily decent FPGAs usually have a programmable PLL. So use it.

But as a disclaimer I'm not sure about your question. I'm saying these after seeing questions about multiple clocks.
 

you can mix clock domains just fine - as long as you get the data across the boundary safely - eg. using a dual clock FIFO.

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And going from slow to fast means you wont ever overflow the FIFO.
 

I feel tempted to mention that we don't like pure link answers at Edaboard.

djnik1632 is asking a specific question and the link doesn't actually answer it. I believe that the link gives a basic explanation about multiple clock domain setups, but the OP is asking about a best solution for the said frequency combination.

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You might find out that 50/18.432 = 128*9/3125. A special PLL would be able to derive one from the other clock. But in your design, they have to be treated as asynchronous clocks anyway. In so far, it's not important from the domain crossing viewpoint, if they are sourced from different clock oscillators which is probably the most simple solution.
 

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