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How to encrypt VHDL package file & synthesis with it

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Hello all,

I want to be able to encrypt a vhdl package.

The package contains sensitive contants etc

I've seen modelsim `protect before, however I have no idea where the guide on it is... my google-fu isn't what it used to be.

I mainly want to know if I can synthesis the encrypted file with Vivado.
Does Vivado have it's own method of encryption.

Regards,
Wes
 

There is a discussion about Vivado encryption of source code. The problem is Xilinx has not release their public keys for IEEE-P1735. They only release them under NDA and with justification for the requirement (e.g. you are an IP core vendor).

See this thread on Xilinx's forum.
 

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