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conversion from vhdl to verilog

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meeraamrita

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hi,
how do i convert
generic(alu_type : string := "DEFAULT"); in vhdl to verilog.
 

In the module declaration
Code: 
module module_name #(
 parameter alu_type ="DEFAULT",
// other module parameters
) (
);
or in the instantiation
Code: 
module_name #(
.alu_type("DEFAULT"),
// other module parameters
) instance_name (
);
 
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