Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[Moved]: Write Address Collision

Status
Not open for further replies.

divya narula

Newbie level 3
Joined
Feb 28, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,297
I have a memory with two write ports W1 & W2 writing at the posedge of clk.
What will happen if both have same address at same time ( assuming write enable is high for both ).
 

The data at that location will be corrupted, in a simulation this will result in X's being stored in that location, in hardware you'll end up with a random mix of the data from both writes. The basic rule is Don't Do That!
 

I have a memory with two write ports W1 & W2 writing at the posedge of clk.
What will happen if both have same address at same time ( assuming write enable is high for both ).
It will behave according to the datasheet. A reasonable outcome is simply that data from one port will be used.

Are you talking about a physical memory IC, or memory embedded within an FPGA?

Kevin Jennings
 

It will behave according to the datasheet. A reasonable outcome is simply that data from one port will be used.

Are you talking about a physical memory IC, or memory embedded within an FPGA?

Kevin Jennings



"Is there any protocol followed when such situations happens in IC ? Does write ports have any priority ? "

- - - Updated - - -

Is there any protocol followed when such situations happens in IC ? Does write ports have any priority ?
 

Hi,

I assume it's an IC. Then all the answers are in the datasheet or related application notes.

Every dual port ram has the same problem. Some handle this with a "write collision interrupt", maybe some have priority.

--> Read the datasheet. Everything else is guessing.

Klaus
 

The datasheets I've seen usually say that if you write to both ports of a dual port RAM at the same address the results are indeterminate not one port having priority over the other, or they never even mention what results to expect. Only in cases where the clocks to the dual port are skewed enough that the write setup/holds don't interfere with each other allowing both writes to complete correctly, which means the second one wins (though the OP specified a single clock, clk).

I'm think that there may be confusion over the fact that writing and reading the same address usually favors the read or the write or the priority may be programmable like Xilinx's: read before write, write before read, and no change options.
 
From personal experience -- don't assume! Read the datasheet. Xilinx likes to use "read-first" and "write-first", but these are misleading if you read (or don't read...) the datasheets!

The "read-first" and "write-first" labels in Xilinx devices are misleading as they apply to the data-in and data-out of a single port.
 

The basic rule is Don't Do That!

From personal experience -- don't assume!

I wasn't assuming, I was pointing out that perhaps others "think" that the read first write first stuff had something to do with the write order from multiple ports.

The Xilinx documentation only states that you should never try and write from both ports of a TDP at the same time. It also states that the read first and write first behave identically for TDP (on both ports and between ports) as it does in SDP, this is from UG473. I recall, but have not verified that there were similar conflict avoidance stipulations in the V5-V6 devices too, along with a very similar behavior with respect to the read first write first behavior between the two TDP memory ports.

Also FIFOs are not implemented in Xilinx using single port memory, but use a simple dual port where one of the independent ports is write only and the other is read only. In this case the read first and write first apply just as they do with a single port. So I'm not sure what your experience has been in regards to this topic, that makes you think the read first write first does not apply to a TDP memory.

But getting back to the OPs original topic...As I quoted above my basic rule is don't have address conflicts in the first place. By design I avoid that situation, so I don't have a lot of first hand experience in what happens if you do violate that rule, unlike others it seems.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top