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ref arguments can only be used in routines with automatic storage. Why?

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jdshah

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As far as I understand Static storage is memory created for the variable once and it will remain till end of simulation.
Automatic storage is stack memory created every time subroutine or block called and deallocated when subroutine or block execution is over.

Argument pass by reference share the same memory with caller and sub routine. So it will be better is ref argument is passed to routine with Static storage as static storage will not create stack memory for every call. And multiple call to same routine can change the value at same memory location.

I am confused here. Please help.
 

jdshah said:
As far as I understand Static storage is memory created for the variable once and it will remain till end of simulation.
Automatic storage is stack memory created every time subroutine or block called and deallocated when subroutine or block execution is over.
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This is true, but there is a difference between a routine with a static lifetime versus an automatic lifetime. You should only be using routines with automatic lifetimes. There is no call stack for a routine with a static lifetime See this link.

The reason for this restriction is that Verilog allows you to access the arguments of a routine with a static lifetime from outside that routine, just like any other static variable. If you try to access that argument before the routine is called, the argument would have a bad reference. You would have the same problem if you tried to access the argument after the routine was called and the actual argument from the last call had disappeared.

I suppose SystemVerilog could have made another rule that did not allow you to access ref arguments of a routine with a static lifetime, but I think everyone wants people to stop using routines with static lifetimes.
 
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    jdshah

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As far as you are asking about System Verilog for hardware synthesis there's no point of memory allocation or stack storage of variables because the Verilog code is translated to logic cells and registers. Static variables can be used to implement specific code behavior but are rarely used.
 

dave_59 said:
This is true, but there is a difference between a routine with a static lifetime versus an automatic lifetime. You should only be using routines with automatic lifetimes. There is no call stack for a routine with a static lifetime See this link.

The reason for this restriction is that Verilog allows you to access the arguments of a routine with a static lifetime from outside that routine, just like any other static variable. If you try to access that argument before the routine is called, the argument would have a bad reference. You would have the same problem if you tried to access the argument after the routine was called and the actual argument from the last call had disappeared.

I suppose SystemVerilog could have made another rule that did not allow you to access ref arguments of a routine with a static lifetime, but I think everyone wants people to stop using routines with static lifetimes.
Click to expand...


Hi Dave,

I have following queries. It will be very helpful if you can answer inline.

1. Function or task with automatic lifetime, will create multiple call memory, if called at same time. yes or no

2. Function or task with static lifetime, will create single call memory, if called at same time. And values updated for the variables in function would have final value (for all call). yes or no

3. Class have function and task with automatic lifetime by default. Module has the same with static lifetime by default.

4. What is lifetime and lifetime qualifier.

5. What it make difference, if I put keyword static (or automatic) left to function and right to function.


Please clear my queries, it will be great help.
 

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