why this error happen?

JKR1 · Oct 11, 2015

hi
why this error happen?

TrickyDicky · Oct 11, 2015

This code describes a dual edge flip flop which cannot be done inside an fpga

imbichie · Oct 12, 2015

"wait" statement cannot be synthesis ...

TrickyDicky · Oct 12, 2015

imbichie said:
"wait" statement cannot be synthesis ...

Yes it can, but its not the recommended style. The following will synthesise to a register:

Code VHDL - [expand]
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process
begin
  wait until rising_edge(clk)
  q <= d;
end process;