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Bit masking in System Verilog

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degalabalaji1992

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What is meant by Bit Masking when we are taking 8-bits of Address i want to mask some of the bits which are not considered while evaluating Address?
 

I checked the LRM but didn't find anything that was specifically SV about bit masking?

bit masking is usually just some and operation with a mask to remove some bits from consideration
e.g.
Code: 
parameter mask 8'hF0;
assign decode_c = (addr & mask) == 8'hC0;

In this example we are looking for the addresses that fall between 0xC0 - 0xCF
 

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