legendbb
Member level 1
Just wondering if using always @(posedge clk) and nonblocking assignment for stimuli is at risk of any racing? dut sensitive on the same clock edge, tb:always block is the same as any part of synchronous design.
An example from Doulos shows using clock block with specified skew.
http://www.doulos.com/knowhow/sysverilog/tutorial/clocking/
http://www.testbench.in/TB_16_RACE_CONDITION.html
says if driving is done at posedge and reading in DUT at the same time, it's race (I think the author meant to this example with blocking statement).
Can we pretend TB to be part of DUT in synchronous design?
Also I've seen numbers of examples using specified delays. I used to use @(negedge clk) in initial block. I could have used always @(negedge clk), don't notice any difference in simulation.
Please comment,
:?:
An example from Doulos shows using clock block with specified skew.
http://www.doulos.com/knowhow/sysverilog/tutorial/clocking/
http://www.testbench.in/TB_16_RACE_CONDITION.html
says if driving is done at posedge and reading in DUT at the same time, it's race (I think the author meant to this example with blocking statement).
Can we pretend TB to be part of DUT in synchronous design?
Also I've seen numbers of examples using specified delays. I used to use @(negedge clk) in initial block. I could have used always @(negedge clk), don't notice any difference in simulation.
Please comment,
:?:
Last edited: