Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Analog Circuit demystification

Status
Not open for further replies.

karthik242

Newbie level 2
Joined
Oct 4, 2015
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
18
Untitled.png
Can anyone explain me how the voltage at the highlighted portion is 586mv , vth and veff are shown in the image.Thankyou.
 

Why shouldn't it be? You have a matched current sink at
the source, the gate terminal is biased at the same voltage
as what makes the current in the MOS-diode stack, the
only difference is Vds which is pushing the source up a little
as channel shortens.

Were you expecting perfect matching with imperfectly
matched terminal voltages, or something? Make vdd=1.213
and see matching come around.
 
Why shouldn't it be? You have a matched current sink at
the source, the gate terminal is biased at the same voltage
as what makes the current in the MOS-diode stack, the
only difference is Vds which is pushing the source up a little
as channel shortens.

Were you expecting perfect matching with imperfectly
matched terminal voltages, or something? Make vdd=1.213
and see matching come around.

Thankyou sir, I am not expecting perfect matching. But I am finding the node voltages of the circuit and I am not able to find how the node voltage at highlighted portion is 586mv.On the other side the node voltage is 560mv and is by the calculations vgs-vt=veff, where vg is 1.213, vt is .603v and veff is 0.048v by substituting I got vs(voltage at source) as .56v but on the other hand I am not able to find the node voltage at source by calculations. can u please explain how the voltage at the source is .586v by calculations.
 

I'm not sure there's a convenient equation for it; it's about
the difference in Vgs required, for current in saturation vs
edge of linear region. I suppose you could take the two
equations for Id(Vgs) and declare them equal (assume current
mirror match is near ideal, and it's all the cascode device's
fault) but the problem is that the MOS diode is on the edge
between linear and saturation, where neither equation is
likely to be a good fit (even if at this geometry, either is,
when closer to canonical conditions). I think solving the
two equations for Vgs independently would show you the
difference, just not that accurately.
 

You'll find a detailed discussion of the cascode current mirror in analog design text books, e.g. Razavi, Design of Analog Integrated Circuits section 5.2.
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top