Offloading for memory throughput?

vGoodtimes said:

Did you check to see if the memphy on your device supported DDR4?

Normally the high bandwidth memory uses 4:1 clocking. This means the logic runs at 312.5MHz, and the IO at 625MHz DDR. This works for DDR4 as it is burst oriented, and commands can be issued at a lower rate. If the controller has an 8:1 mode, this would be 156.25Mhz to get 625MHz.

That said, the calibration procedure and signaling requirements may be different enough to matter if you attempt to use a non-DDR4 controller with DDR4 devices.

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Not supported, you have to have a pretty pricy FPGA from Altera's point of view. I knew this getting into it, but figured it would not be too hard to format the commands when set on organizing the reads.

On first glance I thought 1600 would be the next step up 400*4, but it seems that is not the case. "Else it would make it there"
Afaik, the data is on both edges as well as the clock. The pll can get faster I suppose.

I personally would be totally agnostic of other people's writings. And the DDR4 can overlap it's reads. It has it's own pin for that. To me that would be very hard to get working. (ooh, and auto self calibration is added to the DDR4)

ah, ok. Perhaps you should try to look at the algorithm then. It is often possible to select a better data structure or data layout. Likewise, effective caching can be a big help in some applications.

vGoodtimes said:

ah, ok. Perhaps you should try to look at the algorithm then. It is often possible to select a better data structure or data layout. Likewise, effective caching can be a big help in some applications.

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I'm going to figure out a new module to put on there, no harm done in having to reroute things for the 4th time.
I do like to think about more radical options tho, like using massive IO with another PLD in between (for a direct interface simulator). But would over extend my FPGA IO for 64IO +address+ command lines/identifier.