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Implementing an AES cryptographic algorithm

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Binome

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Hi,
I need to implement a VHDL AES algorithm on a DE0-Nano boad. As I'm not a cryptographic expert I'd like to find an existing and easy-to-use implementation. I've found several on the internet but I don't know which one I should use.
Can someone tell me what is important to look at or if they know a good implementation I could use?
Thanks.
 

I think you can trust the ones at opencores.org under the section "Crypto core". Best would be to go with the OCCP certified ones (personally I have never used any of them).
 

Binome,

First you need to understand what your requirement is.

What size key are you going to be using?

Are you going to be using EBC, CBC ...etc mode.

Open cores has some crypto cores that allow variable keylength. I believe they are EBC mode, however you can easily turn them into CBC by chaining (xor previous output with new input)

CBC is more secure because if you have a repeating 128 bit input with EBC mode then a pattern starts to emerge.


When testing you can generate your test vectors and validate them with the following website
http://aes.online-domain-tools.com/
 

I don't really have hard requirements, it's for testing. The 128-bit keysize seems more frequent and the operating mode is whatever. I need something that could be incorporated in a simple top-level design and used in no time.
 

there are so many cores in opencores which are supporting 128 bit but they are with out any modes, under the name of crypt to core.
 

I've downloaded avs_aes as it's certified (another one is certified but it's in verilog and I'm using VHDL). For now I can't find a simple explanation on what I should do to use it (a chronogram for example). I'm reading the documentation...
 

Binome said:
I've downloaded avs_aes as it's certified (another one is certified but it's in verilog and I'm using VHDL). For now I can't find a simple explanation on what I should do to use it (a chronogram for example). I'm reading the documentation...
Click to expand...

yes, mostly you can find verilog cores, if you want to understand the AES implementation NIST FIPS 197 is the standard documentation.
 

Yes I've mostly understood that standard but I'd like to have a component implementing it.
 

There shall be AES variable keylength...try that core
 

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