[SOLVED] SystemVerilog Interfaces

interface u0if ;
logic clk,rst;
logic read;         // bus read operation
logic [7:0] addr;   // device address
logic [7:0] din;    // bus data to UART
logic write;        // write operation
logic [7:0] dout;   // bus data from UART
logic txir;         // transmitter interrupt request
logic txack;        // Acknowledge for txir from CPU
logic rxir;         // receiver interrupt request
logic rxack;        // rxir acknowledge
logic tcir;         // transmitter complete interrupt request
logic tcack;        // ack for transmitter complete
logic txdata;       // UART data out
logic rxdata;       // UART data in


clocking CB @(posedge clk );
  output #1 rst,read,addr,din,write,tcack,txack,rxack;
  input dout,txir,rxir,tcir;
endclocking

modport dw(input txir,rxir,tcir,txdata,
            rst,read,addr,din,write,clocking CB,
            output rxdata);
modport u0(input clk,rst,read,write,din,addr,
        txack,rxack,tcack,rxdata,
    output dout,txdata,txir,rxir,tcir);

endinterface : u0if

`timescale 1ns/10ps
module uart (u0if pins);

logic a = pins.read;

logic b = pins.write;
logic c = pins.txack;
logic d = pins.rxack;
logic e = pins.tcack;
logic f = pins.tcir;
logic g = pins.clk;
logic h = pins.rst;
logic i = pins.addr;
logic j = pins.din;
logic k = pins.rxdata;

assign pins.dout = 7'b0000000;
assign pins.txir = 1'b0;
assign pins.rxir = 1'b0;
assign pins.tcir = 1'b0;
assign pins.txdata = 1'b0;

endmodule

interface intf_AB; 
logic        ack;
logic        ready;
logic        send; 
logic [31:0] data;
endinterface   

module moduleA (  input   bit clk 
                , intf_AB     intf1
		);

endmodule