Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] FinFET circuit design for DPA

Status
Not open for further replies.
L

Lijitha Vegi

Newbie level 2
Joined
Apr 2, 2015
Messages
2
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
11
Is there a way that I can measure dynamic power variance and leakage power variance separately for a given FinFET based circuit?
 

I think you can analyze the leakage power variance (vs. voltage ?) alone if you don't clock the circuit.
 

I am not using a clock. I have a universal logic cell which I'll use in the design of combinational and sequential circuits.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top