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How to bring an internal signal of a module into test bench ?

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msdarvishi

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Hello,

I am working on a design that a Linear Feedback Shift Register (LFSR) is providing a sigal for a module connected to nits output. Now, I am going to bring the LFSR signal into the Testbench and make a delay on one of its cycles and see its effect on the consequent module behavior. I am wondering a way to bring such a signal into the testbench as of my purpose.

Any kind help is cordially appreciated.

Regards,
 

The easiest way is hurray to bring it out via normal port mapping.

With verilog and vhdl 2008 you could use hierarchical signal names to get the signal
 
This question has been lingering in my mind for quite sometime.

I know how to do it in Verilog, e.g. below.
Code: 
if (te0630_top_inst.cpu_top_inst.i_core_top.i_pipeline_top.i_alu_top.of_ex_operation_opcode.mnemonic ==  
    ALU_CMD_STOP) begin
          $display (...something...);
end

I am also aware that in old style VHDL port mapping has to be done to bring out a signal which will not look as elegant as when the same is coded in Verilog.

With verilog and vhdl 2008 you could use hierarchical signal names to get the signal
Click to expand...
So is it done in a similar fashion in VHDL-2008 (have no experience in this)?
 

Thanks for your reply. Maybe you did ot get my point !! I know PORT MAP and its utilization but I am not about to see the signal in the output window. Indeed, the LFSR is producing a signal and feeds it into another module. I am wondering to be able to control this signal manually at the testbench and create a delay in it and see how it affects the functionality of the sequence module.

Regards,









dpaul said:
This question has been lingering in my mind for quite sometime.




I know how to do it in Verilog, e.g. below.
Code: 
if (te0630_top_inst.cpu_top_inst.i_core_top.i_pipeline_top.i_alu_top.of_ex_operation_opcode.mnemonic ==  
    ALU_CMD_STOP) begin
          $display (...something...);
end

I am also aware that in old style VHDL port mapping has to be done to bring out a signal which will not look as elegant as when the same is coded in Verilog.


So is it done in a similar fashion in VHDL-2008 (have no experience in this)?
Click to expand...
 

Sorry my intention was not to hijack your thread.
But since you have mentioned
I am wondering a way to bring such a signal into the testbench as of my purpose.
Click to expand...
, so was my reply accordingly!


I know PORT MAP and its utilization but I am not about to see the signal in the output window
Click to expand...
.
By "output window" do you mean your simulation o/p window?
 

msdarvishi
,

For this kind of experimentation, it is best to modify the DUT by breaking the signal between the two registers into two signals, and re-make the connection in your testbench.

Sometimes you can use the Verilog force statement to override the input to a register, but this also overrides the output of the previous register. So to create your delay, you would have to re-create that register in your testbench by sampling all the inputs to that register.
 

msdarvishi said:
Thanks for your reply. Maybe you did ot get my point !! I know PORT MAP and its utilization but I am not about to see the signal in the output window. Indeed, the LFSR is producing a signal and feeds it into another module. I am wondering to be able to control this signal manually at the testbench and create a delay in it and see how it affects the functionality of the sequence module.

Regards,
Click to expand...

You really should only drive signals that come out at the top level, not forge signals that are internal to the design. That is really for injecting error s.

- - - Updated - - -

dpaul said:
So is it done in a similar fashion in VHDL-2008 (have no experience in this)?
Click to expand...

2008 introduced the<<>> wrappers to do hierarchical referencing. Eg

<< signal module1.module2.signal : Signal_type>>
 

Yes, I mean the simulation window...


dpaul said:
Sorry my intention was not to hijack your thread.
But since you have mentioned , so was my reply accordingly!


.
By "output window" do you mean your simulation o/p window?
Click to expand...
 

Just select the entity from the sim tab.
Then pick the signals you want from the objects window.
But during internal values is not a recommended way of doing things.
 

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