Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Random clock period in a FPGA

Status
Not open for further replies.
B

Binome

Full Member level 3
Joined
Nov 16, 2009
Messages
152
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,298
Location
Lyon, France
Activity points
2,405
Hi,
let's say I am able te get a signal Rand (or a variable or something). Can I have a clock with Rand for period and so different at each clock cycle?
I know the rising and falling edges have to be special and I don't know if it's feasible.
What I want in the end is a clock signal with a period that is random and changing all the time.
 

Hi,

it is possible to generate a pseudo random generator. You may use it´s output to generate a new signal.
Inside the FPGA you shouldn´t call this a "clock", because a clock is considered to be stable with a defined frequency and constant duty cycle.
You may call it a "clock enable" signal.

Outside the FPGA you surely may call it a clock.

It depends on what you FPGA source clock is, what the expected output frequency range amd duty cycle range is. (You may also specify min and max time for LOW and HIGH time)

If the frequency range is small, you may also call it a spread spectrum clock/signal.

***
Tell us more.

Klaus
 

Lets try to understand the design...
I am assuming that your system clock is a normal sq. wave signal with 50% duty cycle.
What I understand is that this signal Rand is having variable HIGH and LOW duration which is random in nature.
What I don't understand is how would your resultant signal vary? Will the period of the resultant signal depend on the HIGH time or LOW time of the Rand signal?
 

Rand is only a random value (integer, std_logic_vector, whatever). Each time it varies I'd like my new "clock" to have it as its period time with a 50% duty cycle.
 

It's feasible if high and low periods of your clock are an integer multiple of a FPGA internal fast clock period, achievable timing resolution depends on hardware features of your FPGA family. What are your requirements.
 

I have no requirement, I just want to know how to do it. I can use bounds to make the variable acceptable but if it has to be a multiple then the "clock enable" method seems to be better.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top