Debdut
Full Member level 3
I have a question which I don't know is valid or not.
In a Charge Pump PLL, the D flip flop based Phase Frequency Detector (after reference and divided frequency outputs get locked in phase and frequency) generate periodic spikes in the UP and DOWN outputs. These outputs are applied to the the gates of the pMOS or nMOS present in the Charge Pump.
My question is whether these pMOS or nMOS devices will survive for long duration if these narrow spikes appear repeatedly at their gates?
Overall, will any MOS survive if narrow spikes appear at their gates for long duration?
In a Charge Pump PLL, the D flip flop based Phase Frequency Detector (after reference and divided frequency outputs get locked in phase and frequency) generate periodic spikes in the UP and DOWN outputs. These outputs are applied to the the gates of the pMOS or nMOS present in the Charge Pump.
My question is whether these pMOS or nMOS devices will survive for long duration if these narrow spikes appear repeatedly at their gates?
Overall, will any MOS survive if narrow spikes appear at their gates for long duration?