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Simulating a bi-directional port

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mauromj

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I am using VHDL to try and simulate an I2C master and slave.

My slave has an inout port named i2c_sda.

My master has a in port named i2c_sda_in and a output port named i2c_sda_out.

In actual hardware, this assignment is very easy to do. All that needs to be done is the following:

Code dot - [expand]
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i2c_sda <= '0' when i2c_sda_out = '0' else 'Z';
 
i2c_master_instance : i2c
port map
(
  master_sda_in  => i2c_sda,
  master_sda_out => i2c_sda_out
)


This does not work however for simulations. What is the work around for this? I have attempted to "switch" between the assignments using a mux but have not found a working solution yet.

Thanks
 
Last edited by a moderator:

This does not work however for simulations.
Click to expand...
As it's nicely mentioned in Edaboard forum rules Only you know what "doesn't work" means... Please clarify.

Presumed the slave is also modelling an open drain output, you have to add a weak pull-up driver in the testbench. If the slave is not clearly driving '0' and 'Z' only, a resolution function may be needed to connect both ports.
 

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