Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Simplest programm JHDL Java for Xilinx Artix 7

Status
Not open for further replies.
J

junior_hpc

Newbie level 1
Joined
Aug 3, 2015
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
35
Hello. I'm trying to write my first program in JHDL (Java) for my Xilinx Artix 7 ac701.
The program must switch on a LED by pressing a button on my FPGA.

First I write my Java code. In the Java code I define an input named a and one output named led. The method on() has to switch on the LED by setting to 1 the output led.

Code Java - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

import byucc.jhdl.base.*;
import byucc.jhdl.Logic.*;
 
public class LEDon extends Logic {
  
  public static CellInterface[] cell_interface = {
    in("a", 1), out("led", 1)
  };
  
  private Wire a, led;
  
  public LEDon(Node parent, Wire a, Wire led) {
    
    super(parent);
    
    this.a = connect("a", a);  
    this.led = connect("led", led);
  }
  
  
  public void on() {
    if (a.get(this) == 1) {
        led.put(this, 1);
    } 
  }
    
}


After that I generate the netlist with JHDL and I obtain the following netlist (.edn):
Code  - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

(edif LEDon
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2015 7 31 10 35 28)
      (program "BYU-CC's JHDL-EDIF netlister by Peter Bellows and Eric Blake"
        (version "0.3.46-internal-development"))))
  (library LEDon
    (edifLevel 0)
    (technology (numberDefinition (scale 1 (E 1 -12) (unit CAPACITANCE))))
    (cell (rename ibuf "ibuf")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port i  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell (rename obuf "obuf")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface
          (port i  (direction INPUT))
          (port o  (direction OUTPUT))
        )
     ))
    (cell (rename LEDon "LEDon")
      (cellType GENERIC)
      (view view_1
        (viewType NETLIST)
        (interface)
        (contents
          (instance a_IBUF
            (viewRef view_1 (cellRef ibuf)))
          (instance led_OBUF
            (viewRef view_1 (cellRef obuf)))
 
          (net (rename led_OPAD_OUT "led_OPAD_OUT")
            (joined
              (portRef o (instanceRef led_OBUF))))
          (net (rename a_IPAD_IN "a_IPAD_IN")
            (joined
              (portRef i (instanceRef a_IBUF))))
          (net (rename led "led")
            (joined
              (portRef i (instanceRef led_OBUF))))
          (net (rename a "a")
            (joined
              (portRef o (instanceRef a_IBUF))))
        )
     ))
  )
  (design ROOT
    (cellRef LEDon
      (libraryRef LEDon)))
)


After that I create on Vivado 2015 a new post-synthesis project and I import the .edn file previously generated and I create a new constraint file (.xdc):
Code  - [expand]
1
2
3
4
5

set_property LOC M26 [get_ports led]
set_property LOC T5 [get_ports a]
 
set_property IOSTANDARD LVCMOS33 [get_ports a]
set_property IOSTANDARD LVCMOS33 [get_ports led]


The problem is when I try to generate the bitstream with Vivado because I get the following error:"[Place 30-494] The design is empty".
Resolution:"Check if opt_design has removed all the leaf cells of your design. *Check whether you have instantiated and connected all of the top level ports."

Do you have any idea where I am wrong? Well, I know how to do it in VHDL with Vivado, but I cannot figure out what's wrong with JHDL.

Thanks in advance.
 

Java HDL?!!
I'm speechless.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top