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[SOLVED] what is wrong with the following code

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hulk789

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Code: 
`define print(v) \
    $display("var v=%h",v)

module try();
reg [3:0] test1='1;
`print(test1);
endmodule
`print(test1);
|
ncvlog: *E,EXPENM (1.sv,6|12): expecting the keyword 'endmodule' [12.1(IEEE)].
get the following error
 
Last edited by a moderator:

Your code looks very confusing and I have never seen something like you have posted above.
Are you clear on what you are doing and what you want to achieve? Do you want to use a Verilog compiler directive?

`define is a compiler directive used for defining text MACROS; this is normally defined in a verilog file "name.vh", where name can be the module that you are coding.
 
Last edited:

dpaul said:
Your code looks very confusing and I have never seen `define being used as you have shown above.
Are you clear on what you are doing and what you want to achieve?

`define is a compiler directive used for defining text MACROS; this is normally defined in a verilog file "name.vh", where name can be the module that you are coding.
Click to expand...
can you give a simple example how would you do the thing with filenames and code in it
 

Off hand I only see that you are using the SV \

Here is a nice presentation on define preprocessor stuff, that might help you get this right.
 

i have written these lines in try.vh
Code: 
`define print(v) $display("var v=%h",v)
and these lines in try.sv
Code: 
module try();
reg [3:0] test1='1;
`print(test1);
endmodule
still i get the same error
 

hulk789 said:
can you give a simple example how would you do the thing with filenames and code in it
Click to expand...

Even though I have not completely understood the "thing" you want, given below is an example of name.vh file which contains the defines.
Code: 
`ifndef EXTERNAL_CONSTANTS_VH
`define EXTERNAL_CONSTANTS_VH

// Define if AXI BFM is connected in top-level design
`define AXI_BFM

`define SOMETHING_ELSE

Then in your Verilog code the defines are used such as:
Code: 
`include "timescale.v"
`include "name.vh"

module my_design_module (
// ports come here
);
// parameters
// HDL logic
.
.
`ifdef AXI_BFM // If AXI_BFM is defined in any of the include files then this is compiled
  // do something
`else              // If the AXI_BFM definition is missing then this part is compiled
  // do something else
`endif

endmodule
 

i am trying to apply this

‘" allows macro SystemVerilog allows argument substitution inside a macro text
argument string by preceding the quotation marks that form the string with a
substitution grave accent ( ‘ ). The example below defines a text substitution
within strings
macro that represents a complete $display statement. The string
to be printed contains a %h format argument. The substituted text
will contain a text string that prints a message, including the name
and logic value of the argument to the macro. The %h within the
string will be correctly interpreted as a format argument.
`define print(v) \
$display(‘"variable v = %h‘", v)
`print(data);
In this example, the macro ‘print() will expand to:
$display("variable data = %h", data);
 

hulk789 said:
i have written these lines in try.vh
Code: 
`define print(v) $display("var v=%h",v)
and these lines in try.sv
Code: 
module try();
reg [3:0] test1='1;  // what is this, a typo? >>>> '1 <<<< 
`print(test1);
endmodule
still i get the same error
Click to expand...

Did you try an example for the presentation instead of your own?

Truthfully I've never been a big fan of `define macros, I think they are overused. They are global across an entire design from the point where they get compiled and can be defined anywhere in the code. Therefore stuff like this can be done which makes things very confusing:
Code: 
file1: `define WIDTH 64
file2: `define WIDTH 16
file3: `define WIDTH 32
file4: uses `WIDTH but doesn't define it
depending on the compile order of file1-3 file4's `WIDTH might be 16, 32, or 64.

If a parameter was used there would be no chance of redefining a define and in your case using a function or task would accomplish the same thing.
 

or at least this

Verilog allows the quotation mark ( " ) to be used in a ‘define
macro, but the text within the quotation marks became a literal
string. This means that in Verilog, it is not possible to create a string
using text substitution macros where the string contains embedded
macro arguments.
In Verilog, the following example will not work as intended:
`define print(v) \
$display("variable v = %h", v)
`print(data);
In this example, the macro ‘print() will expand to:
$display("variable v = %h", data);

- - - Updated - - -

'1 fills all bits on the left-hand side with 1
Code: 
module try();
reg [3:0] test1='1;  // what is this, a typo? >>>> '1 <<<< i think not a typo
`print(test1);
endmodule

- - - Updated - - -

Did you try an example for the presentation instead of your own?
Click to expand...
This is an example form textbook system verilog for design
 

are you compiling with sv enabled in ncvlog?

I know modelsim/viavado/ise don't have sv enabled by default you have to add a switch to enable it. Then again you do have the .sv extension.
 

Although it is a good programing practice, there is no requirement to put `defines in a separate file.

The problem with your code is the macro expands to a $display statement, and the $display statement needs to be inside a block of procedural code. So you need to instantiate a procedural block with an initial construct.


'1 is the only SystemVerilog construct being used in the example. It means fill the assignment to its width with ones. In this case it is the same as 4'b1111 in Verilog.

But I think what you want is

Code: 
`define print(v) \
    $display(`"var v=%h`",v)

module try();
  logic [3:0] test1='1;
  initial `print(test1);
endmodule
 
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