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sample and hold without latch infered

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hulk789

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Code: 
always @ (sample,inp) begin
         if(sample==0 ) begin
             vinp=vinp;
         end
         else begin
             vinp=inp;
         end
    end

is it possible to not infer a latch for a sample and hold type of code in synthesis.
 

No. Anything that has memory will infer a latch.
 

hulk789 said:
is it possible to not infer a latch for a sample and hold type of code in synthesis.
Click to expand...

Yes, a flip flop.

Kevin Jennings

- - - Updated - - -

TrickyDicky said:
No. Anything that has memory will infer a latch.
Click to expand...
You know better than that. Flip flops are memory and they are not a latch (in the context of what a designer would describe and use, not what a flip flop is at the transistor level).

Kevin
 
Anything that has memory will infer a latch.
Click to expand...
Should be read "A memory in combinational always block". I guess.

There are some applications where you intentionally infer a latch, e.g. in some cases, a transparent latch is better suited as address register in a multiplexed processor bus than a flip-flop.
 

And the code specified by the OP is a latch

Code Verilog - [expand]
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always @ (sample,inp) begin // combinational code as FvM mentioned
         if(sample==0 ) begin
             vinp=vinp;  // memory as Tricky mentions
         end
         else begin
             vinp=inp;
         end
    end


Without a posedge or negedge sensitivity on a signal the always block will always infer either combinational logic or a latch (if any outputs are fed back or not defined in a branch).
 
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    dpaul

    dpaul

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ads-ee said:
And the code specified by the OP is a latch
Click to expand...
Yes the OP posted code for a latch, but the question the OP posted is can you not infer a latch for a sample and hold. The answer there is yes, use a flip flop.

Kevin
 
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