need verilog/vhdl code for 7-seg display spartan-3 fpga

Code Verilog - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unSIGNED.ALL;
entity seg is
port ( 
                    
                    SS2_A,SS2_B,SS2_C,SS2_D,SS2_E,SS2_F,SS2_G : out std_logic;
               SS1_A,SS1_B,SS1_C,SS1_D,SS1_E,SS1_F,SS1_G : out std_logic;
                    
                    SW : in std_logic_vector(3 downto 0)
                    );
end dc;
architecture Behavioral of dc is
signal q:std_logic_vector(3 downto 0);
signal DISP1:std_logic_vector(6 downto 0);
begin
q<= SW;
seg1: process (SW)
   case q(3 downto 0) is
   when "0000" => DISP1 <= "1111110"; --0
    when "0001"=> DISP1 <="0110000";--1
    when "0010"=> DISP1 <="1101101";--2
    when "0011"=> DISP1 <= "1111001";--3
    when "0100"=> DISP1 <="0110011" ;--4
    when "0101"=> DISP1 <="1011011";--5
    when "0110"=> DISP1 <=  "1011111";--6
    when "0111"=> DISP1 <="1110000";--7
    when "1000"=> DISP1 <="1111111";--8
    when "1001"=> DISP1 <="1111011";--9
    when "1010"=> DISP1 <="1110111";--A
    when "1011"=> DISP1 <="0011111";--b
    when "1100"=> DISP1 <="1001110";--C
   when "1101"=> DISP1 <="0111101";--d  
   when "1110"=> DISP1 <="1001111";--E
   when "1111"=> DISP1 <="1000111";--F  
    when others => DISP1 <="1111111";   
    end case; 
SS1_A <=  DISP1(6);
SS1_B <=   DISP1(5);
SS1_C <=   DISP1(4);
SS1_D <=   DISP1(3);
SS1_E <=   DISP1(2);
SS1_F <=   DISP1(1);
SS1_G <=   DISP1(0);
END PROCESS;
end Behavioral;