matrixofdynamism
Advanced Member level 2
I have read this marvelous book on processor architecture. It teaches that:
The classic RISC pipeline comprises:
Instruction fetch
Instruction decode and register fetch
Execute
Memory access
Register write back
Now wikipedia says that:
•Many designs include pipelines as long as 7, 10 and even 20 stages (as in the Intel Pentium 4).
•The later "Prescott" and "Cedar Mill" Netburst cores from Intel, used in the latest Pentium 4 models and their Pentium D and Xeon derivatives, have a long 31-stage pipeline.
How can a pipeline be so long? I am in awe and lost as to why we need such long pipelines. Do all instructions need such long pipelines?
Also, since MIPS may implement FPU as well in a coprocessor, how does that effect the 5-stage pipeline? I don't think that a floating point calculation can be complete within a single clock cycle for execute stage.
The classic RISC pipeline comprises:
Instruction fetch
Instruction decode and register fetch
Execute
Memory access
Register write back
Now wikipedia says that:
•Many designs include pipelines as long as 7, 10 and even 20 stages (as in the Intel Pentium 4).
•The later "Prescott" and "Cedar Mill" Netburst cores from Intel, used in the latest Pentium 4 models and their Pentium D and Xeon derivatives, have a long 31-stage pipeline.
How can a pipeline be so long? I am in awe and lost as to why we need such long pipelines. Do all instructions need such long pipelines?
Also, since MIPS may implement FPU as well in a coprocessor, how does that effect the 5-stage pipeline? I don't think that a floating point calculation can be complete within a single clock cycle for execute stage.
