chris06
Newbie level 3
Hello,
I'm using EDI for the PlaceAndRoute flow.
The top-level clock tree is not correctly balanced due to the fact that EDI does not take into account the clock latency Inside the subchips.
Is there a variable to set or a special command to be used in order to balance correctly the clock tree? The information of subchips clock latency is availble in the subchip LIB files (timing_type max_clock_tree_path) so there should be a way to make EDI understand this clock offset.
The workaround that I'm using is to use the following kind of commands for each subchip clock pins but that's not automatic and a bit painfull:
MacroModel pin XXX/YYY/CLK 400ps 400ps 400ps 400ps 0ff
Best regards
Chris
I'm using EDI for the PlaceAndRoute flow.
The top-level clock tree is not correctly balanced due to the fact that EDI does not take into account the clock latency Inside the subchips.
Is there a variable to set or a special command to be used in order to balance correctly the clock tree? The information of subchips clock latency is availble in the subchip LIB files (timing_type max_clock_tree_path) so there should be a way to make EDI understand this clock offset.
The workaround that I'm using is to use the following kind of commands for each subchip clock pins but that's not automatic and a bit painfull:
MacroModel pin XXX/YYY/CLK 400ps 400ps 400ps 400ps 0ff
Best regards
Chris