Explanation of fault models: toggle, transition, delay, IDDQ

fault models

hi;
could you explain these fault models:toggle;transition;delay;IDDQ
thx

Re: fault models

IDDQ:a CMOS circuit would use very little power and that in standby, it would draw practically nothing - just the leakage current.

http://www.qstar.be/html/about_iddq.html

you can use GOOGLE to look up others.

fault models

You can find all of these in the book that I recommended.
Good luck,

fault models

Fault models:

Stuck-At
The stuck-at fault model is the standard model for test pattern generation. This
model assumes that a circuit defect behaves as a node stuck at either 0 or 1.
The test pattern generator attempts to propagate the effects of these faults to
the primary outputs and scan cells of the device, where they can be observed
at a device output or captured in a scan chain.

Transition
The transition delay fault model is used to generate test patterns to detect
single-node slow-to-rise and slow-to-fall faults. For this model, TetraMAX
launches a logical transition upon completion of a scan load operation and
uses a capture clock procedure to observe the transition results. (This feature
is licensed separately.

Path Delay
The path delay fault model tests and characterizes critical timing paths in a
design. Path delay fault tests exercise the critical paths at-speed (the full
operating speed of the chip) to detect whether the path is too slow because of
manufacturing defects or variations.

IDDQ
The IDDQ fault model assumes that a circuit defect will cause excessive
current drain due to an internal short circuit from a node to ground or to a power
supply. For this model, TetraMAX does not attempt to observe the logical
results at the device outputs. Instead, it tries to toggle as many nodes as
possible into both states while avoiding conditions that violate quiescence, so
that defects can be detected by the excessive current drain that they cause.

Bridging
The bridging fault model tests for shorts between two normally unconnected
instance pins or net names. This model reports candidate defects as types
bridging fault at 0 (ba0) or bridging fault at 1 (ba1), and victim and aggressor
node sets.

For more detailed information, pls refer to the SOLD: TetraMAX® ATPG User
Guide