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What does exactly clock latency mean?

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shelkerahul

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HI,

Can any body tell me what exactly latency means?

Up till now my understanding was, latency will be in terms of clock period. I have seen in design latency of 1000pSec (clock period 5.5nSec).

I am confused please some body help me out

Can i get some papers on it?


Thanks in advance

Rahul
 

what is clock latency

you define an ideal clock when constrain the design(chip),clock latency decribe the difference between the clock pad and ideal wave .
 

set clock latency

there are two type latency in synopsys tools:

1. source latency is the propagation time from the actual clock origin to the clock
definition point in the design;
2. network latency is the porpagation time form the clock definition point in the design to DFF's clk.

when pre-layout: you must set_clock_latency -source .... and
set _clock_latency ......

when post-layout you must set_clock_latency -source .... and
set _propagated_clock ......
tools can auto calculate the network latency.
 

clock source latency

Clock Latency: The difference in arrival times for the same clock edge at different
levels of interconnect along the clock tree.

See doc @
**broken link removed**

tut..
 

clock latency

basically, the clock latency is the delay from the clock root pin (clock source) to the clock leaf pin (such as clock pin of a DFF). Different clock leaf pin may have different latency, which is clock skew.
In design, during pre-layout, you will need to set the clock latency you expected. And after layout, you will need to let the STA tools to calculate each leaf pin's latency and see if there any timing issues caused by the latency.
 

clock latency definition

"set_clock_latency" defines the estimated clock
insertion delay during synthesis.
This is primarily used during the pre-layout synthesis and timing analysis.

After layout, "set_propagated_clock" will make EDA tools calculate the clock latency and skews.

Good Luck
 

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