CPLD dosen't show correctly BCD counter by Verilog

2 digit bcd counter

I just try to design bcd counter (00 to 66) by using verilog. I write verilog code in xilinx and test bench waveform show correctly. Then I try to download to xc9572 cpld. After downloading, when I try to test it start count from 00 to 66 at the first time. Then it back 08 (instead of going back to 00)and later the counter show 08 to 66 only. From 00 to 07 is just disappear after 1st loop.

here is my program:

module contain(vc,ttl,qx,qy);
input vc,ttl;
output [3:0]qx,qy;

wire a,b,c,d,a1,b1,c1,d1;
wire reseta,resetc;

assign resetc=((a&b&c) & (b1&c1));
assign reseta=( (b&d) | ((a&b&c) & (b1&c1)));

ls7493 x1(vc,ttl,reseta,reseta,a,b,c,d);
ls7493 x2(vc,d,resetc,resetc,a1,b1,c1,d1);

assign qx={d,c,b,a};
assign qy={d1,c1,b1,a1};
endmodule
---------
module ls7493(VCC,AA,reset0,reset1,QA,QB,QC,QD);

input AA,reset0,reset1,VCC;
output QA,QB,QC,QD;
wire QA,QB,QC,QD;

reg reset;
always@(reset0 or reset1)
begin
reset = reset0 & reset1;
end
ff A(VCC,reset,AA,QA);
ff B(VCC,reset,QA,QB);
ff C(VCC,reset,QB,QC);
ff D(VCC,reset,QC,QD);

endmodule
-------
module ff(t,rst,in_t,output_t);

input t,rst,in_t;
output output_t;

reg output_t;

initial output_t = 1;
always@(negedge in_t or posedge rst)
begin
if(rst==1)
output_t <= 0;
else if (t==0)
output_t <= in_t;
else
output_t <= ~output_t;
end

endmodule

bcd zähler reset

Instead of using all those scary asynchronous counters and resets, you should redesign using only synchronous counters.

Here is a two-digit synchronous BCD counter that counts from 00 to 66 then back to 00:

t - ff verilog qb

Hi,
I agree with echo47; ur problem is asynch reset and ripple counter.
The problem with ur circuit is async reset pulse width which is not
sufficient to reset qxx[3] flip-flop. qxx[3] gets clk as qxx[2] gets reset from
1->0 it ignores reset and gets set! So the result ur getting!
Hope this helps you understand ur implementation better!

bcd cpld

Yes, I agree with echo47 too. Behavor describe sysnthesisable can simple your design.