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Variable clock generation in verilog using task

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raghavkmr

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I have used following code to generate clock (whichever value i pass through task it will create that frequency), but the code only works if i use CLKSEL_global = clksel_local (line no. 23)(i.e. blocking assignment) but that creates delta delay.

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`timescale 1ns/1ps
module new(CLK,CLK_OUT);
input CLK;
output CLK_OUT;
 
and(CLK_OUT,1,CLK);
 
 
endmodule
`timescale 1ns/1ps
module tb();
real CLKSEL_global;
reg clk;
reg CLK7;
wire clk_out;
 
new dut(clk,clk_out);
 
task task_CLOCK;
 
input real clksel_local;
begin
CLKSEL_global = clksel_local;
 
end
endtask
 
initial begin
 CLK7 = 0;
 forever begin
  #(500.0/CLKSEL_global) CLK7 = 1;
  #(500.0/CLKSEL_global) CLK7 = 0;
 end
end
 
always @(CLK7) begin
   clk = CLK7;
 end
 
 initial begin
task_CLOCK(340.0);
  end
  
 initial begin
 #100 $finish ;
 end
 endmodule


how do i generate variable clock without creating delta delay
 

Re: variable clock generation in verilog using task

I don't get why you generate your clocks with this code.

It's a lot simpler to use a clock module that generates the clock. Then it represents a clock oscillator on a board (the testbench).

I use a generic clock generator module that accepts parameters for either period/frequency, value(either period/frequency), differential/single-ended. It has 2 outputs +/- and 1 input an enable/disable port.

I'd rather write something like the clock generate I use once and never have to write it again, instead of doing what you are doing by adding all that code (a lot of which seems redundant and convoluted) to generate a simple clock at a specific frequency.
 
Re: variable clock generation in verilog using task

how can i pass real values through module that is the problem ,thats why i shiftedto task
 

Re: variable clock generation in verilog using task

Use parameters and assign a real value to it, when you instantiate the module.
 

Re: variable clock generation in verilog using task

And don't forget that for most simulations you perform, your clock should be ideal anyway. This notion of clock frequency in RTL is rarely needed, but often implemented by naive designers/students.
 

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