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VHDL "inout" port map connection between two modules

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blach100

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Hello,

I have a problem connecting two modules, I'm trying to design a stack using single port RAM,
the RAM has an inout port for data, to read from and to write with.

HTML: 
ENTITY RAM IS

PORT (address :in std_logic_vector (15 downto 0);-
- address Input
data :inout std_logic_vector (15 downto 0); --data bi-directional

);
END ENTITY;

The STACK which is the top level module has two signals one input and the other output

ENTITY stack IS

HTML: 
PORT (STin : IN std_logic_vector; --Input Data
reset, clk, push, pop : IN std_logic; -- Reset, Clock, Push,and Pop Signals
STout : OUT std logic vector -- Output Data

END ENTITY;

now, when I try to connect the two modules using port map, I write:
HTML: 
SP_RAM_controler : component SP_RAM
            port map(
                         
		data => STin,
		data => STout,
		
               );

I get an error saying
HTML: 
 Cannot assign to object "STin" of mode IN.

how can I connect the input and output of the stack with the inout signal of the RAM?

thanks
 

If the RAM is an internal RAM - then you should not be using inout ports. Inouts are ONLY for devices that are external to the FPGA using IO buffers. looking at your code, this ram appears to be internal.
 

Either if it's internal or external, the RAM component can't work without read and write control signals that among other purposes control the direction of the inout data port. In so far the code is either incomplete or erroneous.

Interfacing an inout signal to unidirectional in and out ports requires at least a tristate driver for the out port. Its enable signal must be mutual exclusive to the enable signal for any other inout driver.
 

Hello again,
and thank you for your answers,

I solved part of the project using an intermediate signal, between the input of the stack and the inout of the RAM and I'm able to push data into the RAM,
@FvM yes I have some control signal,
but now I can't pop from the RAM,
this is my code:
Code: 
if ( cs = '1') then -- must be equal to one in order to make changes on the RAM

	if (oe = '1') then -- read operation (POP)

		--temp:=to_integer(unsigned(address));
		data <= ram(to_integer(unsigned(address)));
		
	elsif (rw = '1' and oe = '0')then -- write operation (PUSH)
		
		ram(to_integer(unsigned(address)))<= data ;
				
	end if;
else 
	data <= (others=>'Z');
end if;

why can't I read from an std_logic_vector array and put in an std_logic_vector signal ?
Code: 
data <= ram(to_integer(unsigned(address)));

in the simulation I'm getting "000X" in every reading
thanks
 

FPGAs don't have bidirectional signals inside them, therefore this doesn't translate without tri-state to multiplexer transformations being done on your code. It makes more sense to use the inferred RAM templates (which have separate read and write data ports) provide by the FPGA vendor than trying to do something that isn't exactly supported by actual physical hardware resources.
 
well, yes, I have changed the inout port to in and added a new signal as out, and I'm able to pop push from the RAM.
thank you for your answers.
 

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