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He didn't ask a question. He gave you some information. 75 us is 3750 clock periods at 50 MHz (I'm assuming it isn't 50 milliHertz as the diagram indicates).
So design a counter in Verilog that counts to 3750. When it gets there, it outputs a pulse, resets to zero and counts again. That will give you your 75us timing marker.
oh Thanks. But in my diagram the input is 50miliHerts and the output is 75micro second, so I think in the beginning I should change the frequency to time so it will be 20second.
And my question is how I can write the code in Verilog for the same diagram??
Firstly, you are going to have to decide what the actual design problem is. I think it is more likely that there is a typo on your diagram (i.e. should be 50 MHz rather than 50 mhz). 50 mHz and 75 us makes no sense, nor does 50 mHz and 20 seconds.
Secondly, I did explain how you can write Verilog code for this. This is a very simple Verilog exercise, and you should be able to find several examples in books, tutorials and on the internet. Take a shot at writing it and then ask specific questions if you get stuck.
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