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Need help to understand simple error code VHDL

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mrclrn

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Hello guys,

I'm new with VHDL. I'm trying to understand what this error mean :

vhd(20): Cannot read output "s1".
Click to expand...

There is my code:

---------------------------------------
Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
 
entity b1 is
 
  PORT ( a, clk, reset_sync   :in STD_LOGIC;
         s1, s2               :out STD_LOGIC);
END b1;
 
architecture Behavior of b1 is
 
component dff
    Port ( D, clk, reset_sync   : in STD_LOGIC;
           Q        :out STD_LOGIC);
end component;
signal y1:std_Logic;
begin
 y1 <= s1;
 dffa : dff port map (a, clk, reset_sync, y1);
 dffb : dff port map (y1, clk, reset_sync, s2);
end Behavior;


-------------------------
the error is on line 20: y1 <= s1;


Thank you for your help!
 
Last edited by a moderator:

You have defined 's1' to be an output of the entity. Prior to VHDL-2008, outputs could not be read, which means they cannot be on the right hand side of an assignment, so 'y1 <= s1;' is illegal which is the error that is being reported. There are two pre-2008 solutions:
- Define s1 as 'buffer' instead of 'out' in the entity. Then it is legit to use s1 on both the left and the right hand side.
- Define an internal signal (say 's1_internal') and use that everywhere you want. Add an assignment 's1 <= s1_internal' to connect that new signal to the entity output.

Using VHDL-2008 rules, it is much simpler since they have removed that requirement so 'y1 <= s1;' is legal. In the Modelsim project window, right click and you should run across an option to compile it according to the 2008 standard. If you're trying to synthesize the design into an actual part, you will have to do the same thing in that tool to tell it which set of rules to follow. If your tool does not support 2008, then complain to the supplier and tell them you'll be taking your business elsewhere. There have been four major revisions of the language: 1987, 1993, 2002 and 2008.

Kevin Jennings
 

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