[SOLVED] Tool to change a file from synth to simulation values

Hello all,

I'm using vivado & trying to create a script that can change files to and from simulation/synthesiable.

Classic example of the use. You have a constant pacakge that has values for simulation, but different values in the synth product. The values are identified by anchors(i.e --@synth_start/--@synth_end) arround the block of code

The problem I'm getting is that the lsearch feature is falling over vhdl commands like
constant x :std_logic_vector(x downto 0) := "00100";

It appears that the is causing problems with the lsearch.

I've used however this throws all sorts of crazy syntax ;, \, " etc into the line & makes my search freak out.

Anyone know what I can do to get the search working? Without list freaking out at places where there is a quote followed by some other character.

I don't want to change all the possible vhdl files by manually adding a space after the quotations on the line.

I may be able to give sample code & source later, however for now I do not have access to these.

Regards,
Wesley

Not sure why you are going to the trouble of physical modifying the code. In Verilog code I've done I use an ifdef around blocks of code that are different for sim/synth. I just set a SIMUTATION define and add that setting to my testbench. I also do this (or use parameters) for synth options.

VHDL has similar capability using generics.

Regards

Does that mean I can do something like

With


Therefore I only have to change one variable?
Regards,
Wes

wesleytaylor said:

Does that mean I can do something like

Code:

constant synth_condition : boolean := true;
constant sim_condition : boolean;
sim_condition <= not synth_condition

?

Regards,
Wes

Click to expand...

Or more like
constant sim_condition : boolean := (not synth_condition);

Or even more interesting, you could use a function with synthesis translate on/off in it to set the value of the synth constant:

Doing stuff like this avoids the necessity of modifying code through scripts and such, or having separate synthesis and simulation files.

As I've used some sort of source control for VHDL/Verilog code this works very nicely with ensuring both synthesis and simulation settings are always preserved in the source's history. Using something similar with a design I worked on, allowed us to have a common code base for three different design options. I just ran the three builds in different directories setting a top level parameter (Verilog design) to determine what submodules and options were used. I used the ISE/Vivado options to set the parameter in the GUI and my testbench had a setting that could changed by the different testcases.

Regards

Thank you so much guys