Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Fix error in this Verilog code

Status
Not open for further replies.
P

prakhars

Junior Member level 3
Joined
Oct 5, 2012
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,497
I want to assign out an incremented value of integer x at every 100 unit of time. but getting three errors at line #5,... "unexpected token: '='", "unexpected token: '+'" and "expecting 'endmodule', found '1'"

1) module model(out);
2) output reg [2:0]out;
3) integer x;
4) initial x=0;

5) x=x+1;
6) #10;
7) assign out=x;
8) endmodule
 

You need to add begin and end to the initial block. The delay of 10 can be added to the assignment statement itself, something like out = #10 x. This is a better way of writing code.
 

output reg [2:0] out;
will not compile when using
assign out = x;
out must be a wire not a reg.

also if you want to continuously increment x every #10 then you need to add a forever statement around the x = #10 x+1; code.
 

I did following modification and still getting two errors "unexpected token: '='" and "unexpected token: ';'" at line 8.

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9

module model(output wire [2:0]out);
integer x;
initial 
begin
x=0;                                            
forever x=x+1;
end
out=x;
endmodule
 
Last edited by a moderator:

I think this is what want:
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12

module model (
  output  [2:0]   out
);
 
initial begin
  integer x = 0;
  forever x = #10 x + 1;
end
 
assign out = x;
 
endmodule

I didn't notice originally that the out should have been defined as a wire instead of a reg.
You also forgot to add a time control statement to the forever loop, your code wouldn't have run correctly as it would get stuck in the forever loop at 0 ns, incrementing continuously which would have ended up being an iteration limit reached error.

Regards
 

thanx ads-ee for the code,..

but still getting errors
 

X is integer but out is not a integer.
I think this could be the error
 

These are the error at line 6 :-

unexpected token: 'integer'
unexpected token: '='
expecting 'endmodule', found '0'
 

Argh that's what I get for just typing stuff and not checking it. :-(

move the integer declaration outside the initial block.

- - - Updated - - -

You do know that the integer x is nominally a 32-bit value on most platforms (it's actually not explicitly defined in the LRM), so effectively your increment of x is assigned as a modulo of 8 to the out output. i.e. x=0-7, out=0-7; x=8-15, out=0-7; x=(8*n)-(8*n+7), out=0-7

You could just declare x as a reg: reg [2:0] x = 0;
 

Actually, the SystemVerilog LRM defines int and integer to be exactly 32 bits. But your advice is still valid.
 

either with x as an integer or a register getting error, "Unsupported Forever Statement. "
 

what are you using to simulate this with? Or perhaps you trying to synthesize this?

Forever and initial blocks aren't synthesizable. They are for simulation purposes.
 

Ok ok got it,...
I'm using Xilinx ISE

So it means I can't get this thing on FPGA,..
 

If by "this thing" you mean, your exact code, then no. Because it is not synthesizable.

If you mean something that does the same functionality, but for which you (*) are going to be writing the synthesizable code, then yes sure you can get that thing on the fpga.

You may want to read up on what verilog constructs are synthesizable. A healthy assumption to keep in mind while writing verilog is "nothing is synthesizable, except for the things for which I have explicitly checked that they are".


(*) Well, or maybe ads-ee if he feels like it. Small enough example. But personally I'm of the school of thinking that subscribes to "Go Read A Book". ;)
 

Well, I'm not going to give you the code (despite what mrfibble thinks I might feel like doing ;-)), I subscribe to the learn by doing school of thinking.

What you want to do is a google search on Verilog counters. As you will soon discover, counters need clocks, so you need to find what pin the clock on the board comes into your FPGA. (read the documentation for your board).

Once you have designed a counter that counts out enough time to match your "100 time units" you can generate the x = x + 1 count value.

Now run off and do some reading and studying, then come back after you've written something that still breaks your isim simulation.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top