shaiko
Advanced Member level 5
Hello,
When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.
What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?
When instantiating a VHDL component, sometimes Modelsim doesn't allow to leave output ports OPEN while in other cases it does allow that.
What is the rule according to the LRM ?
When is it allowed to leave a component output port OPEN?