vhdl signal definition

Hello,

In my entity there're 3 unconstrained ports.

x in an internal signal to this entity.
I want signal x to have the length of the longest of the above ports.
For example:
If b'length > a'length > c'length
I want x to be automatically defined as:
Can it be done?

shaiko said:

Hello,

In my entity there're 3 unconstrained ports.

Code:

a: in unsigned ;
b: in unsigned ;
c: in unsigned ;

x in an internal signal to this entity.
I want signal x to have the length of the longest of the above ports.
For example:
If b'length > a'length > c'length
I want x to be automatically defined as:

Code:

signal x: unsigned (b ' range )

Can it be done?

Click to expand...

Yes, write a few functions:
- Get_Longest(a, b, c: unsigned) return integer;
- Select_High(a, b, c: unsigned; Sel: integer);
- Select_Low(a, b, c: unsigned; Sel: integer);

Then define x as:
signal x: unsigned(Select_High(a, b, c, Get_Longest(a, b, c)) downto Select_Low(a, b, c, Get_Longest(a, b, c)));

The basic idea is the following:
- 'Get_Longest' will take as inputs your three unsigned and will return a number indicating which one is the longest (i.e. 0 for a; 1 for b; 2 for c)
- 'Select_High' will take as inputs the three unsigned as well the output of the 'Get_Longest' function and return the 'high attribute of the selected input.
- 'Select_Low' will do the same as 'Select_High' but for the 'low attribute.
- Now you define your signal 'x' in terms of the 'Select_High' downto 'Select_Low' functions

You might also want to define constants to receive the two outputs of the 'Get_Longest' function calls and then use those computed constants to define 'x'. The only reason for that is when you have these nested function calls used to define something basic like the array bounds, it can get difficult to see the forest for the trees sometimes. By defining separate constants at least you can see what those constants end up getting computed to be directly in Modelsim, you can also print them out so they get into an output logfile, etc. It's not a big thing, but sometimes it makes debug easier.

Kevin Jennings

Thanks for your help.

I want the functions not to be limited to a specific number of a/b/c...
Can a VHDL function accept a 2d unconstrained array?

shaiko said:

Thanks for your help.

I want the functions not to be limited to a specific number of a/b/c...
Can a VHDL function accept a 2d unconstrained array?

Click to expand...

In general, yes you can, instead of having a, b, c you would input an array of unsigned to the function. But in this particular case it wouldn't do you any good. By definition, all of the elements of a 2d array (or an unconstrained array of unconstrained) would all have the same dimensions so there would be no 'longest' one to choose from so you could pick any element of that array to define the dimensions of x.

Kevin Jennings