[SOLVED] manual routing vs autorouting using ISE

Hello All,

Is manual routing recommended ?

If so , then does any1 have any reliable resource to learn manual routing inside an fpga?

Thanks

As long as the normal tools can fit the design and meet timing, I see no reason to consider manual routing.
If necessary, it is probably a better approach to help the tools by locking parts of the design to specific areas of the chip.

Short answer: no
Long answer: no, dont be silly.

10 years with FPGA, the closest Ive come to manual routing is setting regions for blocks failing to meet timing, with a handfull of registers specifically placed. But this was a demanding timing setup.

For most jobs (99.99%) the problem is your design, not the fitter.

As the others have said:

No, never hand route.

I've been working with FPGAs for 20+ years and I've only performed hand routing in XACT (Xilinx Foundation's equivalent to FPGA Editor) back when I worked on 3000 series parts. During this time Xilinx tools were extremely poor at both placement and routing.

Adders would be spread across large portions of the die sometimes. So hand placement had to be performed. While hand placing and rerouting nets I started noticing poorly routed nets, so I would fix them. Turns out some of the nets that could be routed with minor swaps of LUT inputs and rerouting of a few signals would allow a connection between CLBs that were 3-4 apart to be routed on local routing instead of being routed across the entire die (because it was placed on a long line).

So unless you are working on a legacy Xilinx 3000 series part you don't have to hand route.

Nope, you don't want to hand route. You only want to hand route if you are a silly person, like myself.

In the past I've done some hand / scripted routing for small parts of the design. And roundabout 100% of those times it was because I was mucking about with asynchronous stuff. TDCs, ring oscillators, that sort of thing. You can even make small (or large) antenna circuits that the proper tools would never generate. The idea was to slightly tweak route delays by capacitive loading. And it even worked.

But having said that, this was rather time consuming and wildly impractical for any synchronous design methodology.

So, no, never hand route. The tools will do a better job than you.

Oh another reason you don't want to hand route ... routing congestion. At one time I thought to be clever and super duper optimize a synchronous block. Sooo hand craft everything, hand place yadda yadda. And it even was better than the tool generated version ... almost. Except that I forgot to take the limited routing resources between slices into consideration, so I did not have enough resources with a connect distance of 1, while I had plenty of distance 2 and distance 4 left over. Soooo, lesson learned there. The tools take ALL routing resources into consideration, while you might forget some things.

Actually lesson double learned. 1) I should temper my enthusiasm for optimization, and 2) Xilinx are a bunch of moneygrabbing, uhm, persons. They knowingly castrate the tools so you don't get routing congestion information for spartan6, while they do provide the exact same information for the more expensive virtex6. Not because it's impossible or because this information is not there for spartan6, but because we can make some more money by market segmentation in the tooling area. No customer will ever notice. So I had to write a perl + tcl script to overlay that on top of planahead. B*stards! Making me do all that work.