Real time clock in verilog

santh92 · Sep 12, 2014

HERE, I HAVE SUBMITTED MY PROGRAM FOR REAL TIME CLOCK. BUT, UNFORTUNATELY I AM GETTING SOME ERROR IN THE COUNTING PROCESS. AND, ALSO I AM A BEGINNER FOR VERILOG CODE. IN THIS PROGRAM I TRIED TO DISPLAY THE MINUTES AND SECONDS DATA TO THE SEVEN SEGMENT DISPLAY OF SPARTAN-6 XC6SLX16, FTG 256. PLEASE ANY ONE CAN TRY TO UNDERSTAND MY MISTAKE...

ALSO, I HAVE ATTACHED MY PROGRAM MY PROGRAM ERROR ALSO

Code:

REAL TIME CLOCK:

module RTC( clk, min_h, min_l, sec_h, sec_l);

input clk;

output [6:0] min_h;
output [6:0] min_l;
output [6:0] sec_h;
output [6:0] sec_l;

reg [6:0] min_h;    // MINUTES AND SECONDS WILL BE DISPLAYED IN 7 SEGMENT DISPLAY
reg [6:0] min_l;
reg [6:0] sec_h;
reg [6:0] sec_l;

// EXTRA SIGNALS YOU NEED
reg [3:0]sec_lower;
reg [3:0]sec_higher;
reg [3:0]min_higher;
reg [3:0]min_lower;

integer count;      // SINGLE 32_BIT SIGNED INTEGER
integer count1;
integer count2;
integer count3;
integer count4;
reg clk1;
reg clk2;
reg clk3;
reg clk4;

initial 
begin: process_15
count <= 0;
end
initial
begin: process_14
count1 <= 0;
end
initial
begin: process_13
count2 <= 0;
end
initial 
begin: process_12
count3 <= 0;
end
initial
begin: process_11
count4 <= 0;
end
initial
begin: process_10
sec_l <= 7'b0111111;
end
initial
begin: process_9
sec_h <= 7'b0111111;
end
initial
begin: process_8
min_l <= 7'b0111111;
end
initial
begin: process_7
min_h <= 7'b0111111;
end
always @ (posedge clk)
begin: process_6
count <= count + 1;
if (count <= 10000000)
begin
   clk1 <= ~ clk1;

  count1 <= 1;
  count2 <= 1;
  count3 <= 1;
  count4 <= 1;  
end
else
begin
  count1 <= 0;
  count2 <= 0;
  count3 <= 0;
  count4 <= 0;
end
end
always @ (posedge clk1)
begin: process_5
	       count1 <= count1 + 1;
	       sec_lower <= sec_lower + 1'b1;
			 case (sec_lower)
          4'b0001:
			 if (count1 <= 1)
          begin
				sec_l <= 7'b0000110;    // 1
				sec_lower <= 4'b0010;   // next state
			 end
			 else
			   sec_lower <= 4'b0001;   // same state
          4'b0010:
			 if (count1 <= 2)
			 begin
            sec_l <= 7'b1011011;    // 2
				sec_lower <= 4'b0011;   // next state
			 end
			 else
			   sec_lower <= 4'b0010;   // same state
          4'b0011:
			 if (count1 <= 3)
			 begin
            sec_l <= 7'b1001111;    // 3
				sec_lower <= 4'b0100;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b0011;   // SAME STATE
          4'b0100:
			 if (count1 <= 4)
			 begin
            sec_l <= 7'b1100110;    // 4
				sec_lower <= 4'b0101;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b0100;   // SAME STATE
			 4'b0101:
			 if (count1 <= 5)
			 begin
			   sec_l <= 7'b1101101;    // 5
				sec_lower <= 4'b0110;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b0101;   // SAME STATE
			 4'b0110:
			 if (count1 <= 6)
			 begin
   			sec_l <= 7'b1111101;    // 6
				sec_lower <= 4'b0111;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b0110;   // SAME STATE
			 4'b0111:
			 if (count1 <= 7)
			 begin
			   sec_l <= 7'b0000111;    // 7
				sec_lower <= 4'b1000;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b0111;   // SAME STATE
			 4'b1000:
			 if (count1 <= 8)
			 begin
			   sec_l <= 7'b1111111;    // 8
				sec_lower <= 4'b1001;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b1000;   // SAME STATE
			 4'b1001:
			 if (count1 <= 9)
			 begin
  			   sec_l <= 7'b1101111;    // 9
				sec_lower <= 4'b1010;   // NEXT STATE
			 end
			 else
			   sec_lower <= 4'b1001;   // SAME STATE
			 4'b1010:
			 if (count1 <= 10)
			 begin
			   sec_l <= 7'b0111111;    // 0
				count1 <= 0;
            sec_lower <= 4'b0001;		// NEXT STATE
			 end
			 else
			   sec_lower <= 4'b1010;   // SAME STATE
			 endcase
end
always @ (posedge clk1)
begin: process_4
     count2 <= count2 + 1;
       sec_higher <= sec_higher + 1'b1;
     	    case (sec_higher)
          4'b0001:
			 if (count2 <= 10)
			 begin        
            sec_h <= 7'b0000110;    //1
				sec_higher <= 4'b0010;  // NEXT STATE
			 end
          else
            sec_higher <= 4'b0001;	// SAME STATE		 
          4'b0010:
			 if (count2 <= 20)
			 begin
            sec_h <= 7'b1011011;    //2
				sec_higher <= 4'b0011;  // NEXT STATE
			 end
			 else
			   sec_higher <= 4'b0010;  // SAME STATE
          4'b0011:
          if (count2 <= 30)
			 begin	
				sec_h <= 7'b1001111;    //3
				sec_higher <= 4'b0100;  // NEXT STATE
			 end
			 else
			   sec_higher <= 4'b0011;	// SAME STATE			
          4'b0100:
			 if (count2 <= 40)
			 begin
            sec_h <= 7'b1100110;    //4
				sec_higher <= 4'b0101;  // NEXT STATE
			 end
			 else
			   sec_higher <= 4'b0100;
			 4'b0101:
			 if (count2 <= 50)
			 begin
			   sec_h <= 7'b1101101;    //5
				sec_higher <= 4'b0110;  // NEXT STATE
		    end
			 else
			   sec_higher <= 4'b0101;  // SAME STATE
			 4'b0110:
			 if (count2 <= 60)
			 begin
			   sec_h <= 7'b0111111;    // 0
				sec_higher <= 4'b0001;  // NEXT STATE
				count2 <= 0;
			 end
			 else
			   sec_higher <= 4'b0110;
			 endcase
end
always @ (posedge clk1)
begin: process_3		
	count3 <= count3 + 1;
	 min_lower <= min_lower + 1'b1;
		    case (min_lower)
			 4'b0001:
			 if (count3 <= 60)
          begin
				min_l <= 7'b0000110;    // 1
				min_lower <= 4'b0010;   // next state
			 end
			 else
			   min_lower <= 4'b0001;   // same state
          4'b0010:
			 if (count3 <= 120)
			 begin
            min_l <= 7'b1011011;    // 2
				min_lower <= 4'b0011;   // next state
			 end
			 else
			   min_lower <= 4'b0010;   // SAME STATE
          4'b0011:
			 if (count3 <= 180)
			 begin
            min_l <= 7'b1001111;    // 3
				min_lower <= 4'b0100;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b0011;   // SAME STATE
          4'b0100:
			 if (count3 <= 240)
			 begin
            min_l <= 7'b1100110;    // 4
				min_lower <= 4'b0101;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b0100;   // SAME STATE
			 4'b0101:
			 if (count3 <= 300)
			 begin
			   min_l <= 7'b1101101;    // 5
				min_lower <= 4'b0110;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b0101;   // SAME STATE
			 4'b0110:
			 if (count3 <= 360)
			 begin
   			min_l <= 7'b1111101;    // 6
				min_lower <= 4'b0111;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b0110;   // SAME STATE
			 4'b0111:
			 if (count3 <= 420)
			 begin
			   min_l <= 7'b0000111;    // 7
				min_lower <= 4'b1000;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b0111;   // SAME STATE
			 4'b1000:
			 if (count3 <= 480)
			 begin
			   min_l <= 7'b1111111;    // 8
				min_lower <= 4'b1001;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b1000;   // SAME STATE
			 4'b1001:
			 if (count3 <= 540)
			 begin
  			   min_l <= 7'b1101111;    // 9
				min_lower <= 4'b1010;   // NEXT STATE
			 end
			 else
			   min_lower <= 4'b1001;   // SAME STATE
			 4'b1010:
			 if (count3 <= 600)
			 begin
			   min_l <= 7'b0111111;    // 0
				count3 <= 0;
            min_lower <= 4'b0001;		// NEXT STATE
			 end
			 else
			   min_lower <= 4'b1010;   // SAME STATE
			endcase
end
always @ (posedge clk1)
begin: process_2
   count4 <= count4 + 1;
     min_higher <= min_higher + 1'b1;	
		case (min_higher)
          4'b0001:
			 if (count4 <= 600)
			 begin        
            min_h <= 7'b0000110;    //1
				min_higher <= 4'b0010;  // NEXT STATE
			 end
          else
            min_higher <= 4'b0001;	// SAME STATE		 
          4'b0010:
			 if (count4 <= 1200)
			 begin
            min_h <= 7'b1011011;    //2
				min_higher <= 4'b0011;  // NEXT STATE
			 end
			 else
			   min_higher <= 4'b0010;  // SAME STATE
          4'b0011:
          if (count4 <= 1800)
			 begin	
				min_h <= 7'b1001111;    //3
				min_higher <= 4'b0100;  // NEXT STATE
			 end
			 else
			   min_higher <= 4'b0011;	// SAME STATE			
          4'b0100:
			 if (count4 <= 2400)
			 begin
            min_h <= 7'b1100110;    //4
				min_higher <= 4'b0101;  // NEXT STATE
			 end
			 else
			   min_higher <= 4'b0100;
			 4'b0101:
			 if (count4 <= 3000)
			 begin
			   min_h <= 7'b1101101;    //5
				min_higher <= 4'b0110;  // NEXT STATE
		    end
			 else
			   min_higher <= 4'b0101;  // SAME STATE
			 4'b0110:
			 if (count4 <= 3600)
			 begin
			   min_h <= 7'b0111111;    // 0
				min_higher <= 4'b0001;  // NEXT STATE
				count4 <= 0;
			 end
			 else
			   min_higher <= 4'b0110;
			 endcase

end				 
endmodule

I DON'T KNOW WHERE I DID MISTAKE. PLS CHECK IS THERE ANY SYNTAX ERROR OR ANY TECHNICAL ERROR.

MY PROGRAM ERROR IS:

ERROR:HDLCompiler:1401 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 87: Signal count1[31] in unit RTC is connected to following multiple drivers:
ERROR:HDLCompiler:1379 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 110: Driver 0: output signal count1[31] of instance Flip-flop
ERROR:HDLCompiler:1379 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 87: Driver 1: output signal count1[31] of instance Flip-flop
ERROR:HDLCompiler:1379 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 198: Driver 0: output signal count2[31] of instance Flip-flop
ERROR:HDLCompiler:1379 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 254: Driver 0: output signal count3[31] of instance Flip-flop
ERROR:HDLCompiler:1379 - "D:\prasanth\I HAVE TO TRY\REALTIMECLOCK\RTC.v" Line 342: Driver 0: output signal count4[31] of instance Flip-flop

THANKS FOR CARING ME....... PRASANTH

bking · Sep 12, 2014

I'm not a Verilog person (but can generally follow along), but in this case the error code is telling you what the problem is: signal count1 is being assigned values from different places (multiple processes). You have more than one driving source trying to drive the same signal.

ads-ee · Sep 12, 2014

santh92,

Typing everything in all caps is considered shouting, so avoid doing that in future posts.

bking is correct in that you've assigned signal count1, count2, count3, and count4 in two processes. Looking over your code I suspect you never designed what you are trying to implement. It looks like you just started this by directly typing it all into a text editor.

You should think of this in terms of counters instead of building a set of convoluted FSMs.

A seconds counter:

Code:

always @ (posedge clk) begin
  if (sec_incr) begin
    // count 0-59
    if (sec_cnt < 59) begin
      sec_cnt <= sec_cnt + 1;
    end else begin
      sec_cnt <= 0;
    end
  end
end

The minute one would be identical.

You would then decode the outputs of the counters to produce a seven segment decode of the binary counts.

Code:

always @ (posedge clk) begin
  case (sec_cnt)
    0 : begin
          dec7seg_0 <= 7'b/*whatever the code is for 0*/;
          dec7seg_1 <= 7'b/*whatever the code is for 0*/;
        end
    1 : begin
          dec7seg_0 <= 7'b/*whatever the code is for 1*/;
          dec7seg_1 <= 7'b/*whatever the code is for 0*/;
        end
    //....
    59: begin
          dec7seg_0 <= 7'b/*whatever the code is for 9*/;
          dec7seg_1 <= 7'b/*whatever the code is for 5*/;
        end
end

Another option is to make the second and minute counters BCD so you would have two 4-bit counters for each counter and they would count as 0-9 and 0-5 for the LSB and MSB respectively. This will significantly reduce the size of the dec7seg logic. I'll leave it up to you to work that version out.

I also leave it up to you to decide how to generate the sec_incr and min_incr signals.

You should also try and simulate this instead of just running synthesis on it.

Regards

santh92 · Sep 12, 2014

thanks for ur reply:-|

- - - Updated - - -

thanks for ur guidance...sir, and i am an initial learner for verilog... i'll try to understand it well,....:-(

santh92 · Sep 13, 2014

Real Time Clock in Seven Segment display

Gud mng sir, the above program which clock i have to choose for always block (case sensitive), to count the minute and second process....

and also i am in confusion of this below process, any one can explain me clear.......

Code Verilog - [expand]
1
2
3
4
5
6
7
always @ (posedge clk)
begin
    if (count <= 10000000)  // actually here i am using a clock as 20 MHz and I want to convert the clock as 1 Hz...
  that's why i take 10000000 this much count value.. it's right or wrong.. 
 
  clk1 <= ~ clk1;
 count1 <= count1 + 1;

at what count the clock will get inverse,, at that time the frequency will be what...?

i am in big congusion pls help me to understand....

-------------------------------------------------------

edit:
and also one more doubt.... may i take integer value as a case(integer) expression...

santh92 · Oct 7, 2014

[Merged] Real Time Clock in Verilog by using clock division technique

Code:

// REAL TIME CLOCK  ---------
i really feel very happy, after so many tries finally i got the correct solution to display the time in display of spartan-6 by using clock division technique............ and i am the beginner for verilog may i optimize tis code pls help me....
module RTC_VLOG( clk, led, min_h, min_l, sec_h, sec_l );

input clk;    // ON BOARD CLOCK 20 MHZ TO FPGA

output reg led;   
output reg [6:0]min_h = 7'b0111111; // DISPLAY 1
output reg [6:0]min_l = 7'b0111111; // DISPLAY 2
output reg [6:0]sec_h = 7'b0111111; // DISPLAY 3
output reg [6:0]sec_l = 7'b0111111; // DISPLAY 4

// EXTERNAL SIGNALS
integer count = 0;    
integer count_1 = 0;
integer count_2 = 0;
integer count_3 = 0;
integer count_4 = 0;

always @ (posedge clk)    // SENSITIVITY BLOCK
begin
  
  if (count < 10000000)   // 10000000 COUNTS FROM ONBOARD 20 MHZ CLOCK
   begin
	  count <= count + 1;
	  led <= 1'b0;	       // UPTO 0.5 SEC THE LED WILL BE LOW
	end
 else
  begin
   if (count < 20000000)   // FOR 1HZ
	 begin
	   count <= count + 1;
		led <= ~led;		// LED WILL BE HIGH UPTO 1 SEC 
	 end 
   else
	begin
	 count <= 0;
    if (count_1 < 9)
	 count_1 <= count_1 + 1;
	 else
	 count_1 <= 0;	
    if (count_2 < 59)
	 count_2 <= count_2 + 1;
	 else
	 count_2 <= 0;
    if (count_3 < 599)
	 count_3 <= count_3 + 1;
	 else
	 count_3 <= 0;
    if (count_4 < 3599)
	 count_4 <= count_4 + 1;
	 else
	 count_4 <= 0;
  end
 end
end
/// FOR SEC_LOWER DIGIT		 
always @ (count_1)   // count_1 is in sensitivity list
begin
		 if (count_1 < 1)
		  sec_l <= 7'b0111111;  // 0
		 else
		   begin
			if (count_1 < 2)
			  sec_l <= 7'b0000110; //1
			  else
			    begin
				  if (count_1 < 3)
				   sec_l <= 7'b1011011; //2
				  else
				  begin
				   if(count_1 < 4)
					 sec_l <= 7'b1001111; //3;
					else
					begin
					if(count_1 < 5)
					sec_l <= 7'b1100110;  //4
					else
					begin
					if (count_1 < 6)
					sec_l <= 7'b1101101; //5
					else
					begin
					if (count_1 < 7)
					sec_l <= 7'b1111101;  //6
					else
					begin
					if (count_1 < 8)
					sec_l <= 7'b0000111; // 7
					else 
					begin
					if (count_1 < 9)
					sec_l <= 7'b1111111;  //8
					else
					begin					 					
               if (count_1 < 10)
					sec_l <= 7'b1101111;  //9
end end end end end end end end end
end

////   FOR SEC_HIGHER DIGIT///////////	
always @ (count_2) // COUNT_2 IS IN SENSITIVITY LIST	 
begin
		 if (count_2 < 10)
		 sec_h <= 7'b0111111; //0
		 else
		 begin
		 if (count_2 < 20)
		 sec_h <= 7'b0000110; //1 
		 else
		 begin
		 if(count_2 < 30)
		 sec_h <= 7'b1011011; //2
		 else
		 begin
		 if (count_2 < 40)
		 sec_h <= 7'b1001111; //3
		 else
       begin
       if (count_2 < 50)
       sec_h <= 7'b1100110;  //4
		 else
		 begin
		 if (count_2 < 60)
		 sec_h <= 7'b1101101; //5
end end end end end
end

////// FOR MINUTE LOWER DIGIT  //////////
always @ (count_3)
begin		
		if (count_3 < 60)
		min_l <= 7'b0111111;
		else
		begin
		if (count_3 < 120)
		min_l <= 7'b0000110;  //1
		else
		begin
		if (count_3 < 180)
		min_l <= 7'b1011011; //2 
		else
		begin
		if (count_3 < 240)
		min_l <= 7'b1001111;  //3
		else
		begin
		if (count_3 < 300)
		min_l <= 7'b1100110; //4
		else
		begin
		if (count_3 < 360)
		min_l <= 7'b1101101;  //5
		else
		begin
		if (count_3 < 420)
		min_l <= 7'b1111101;  //6
		else
		begin
		if (count_3 < 480)
		min_l <= 7'b0000111; //7
		else
		begin
		if (count_3 < 540)
		min_l <= 7'b1111111;  //8
		else
		begin
		if (count_3 < 600)
		min_l <= 7'b1101111;  //9
end end end end end end end end end		
end
			

/////// FOR MINUTE HIGHER DIGIT /////////////
always @ (count_4)
begin
   if (count_4 < 600)
   min_h <= 7'b0111111;  //0;
	else
   begin
    if(count_4 < 1200) 
    min_h <=	7'b0000110;  //1
    else
    begin
    if(count_4 < 1800)
    min_h <= 7'b1011011; // 2
   else
   begin
   if(count_4 < 2400)
   min_h <= 7'b1001111;  //3
   else
   begin
   if (count_4 < 3000)
   min_h <= 7'b1100110;  //4
  else
  begin
  if (count_4 < 3600)
  min_h <= 7'b1101101;  //5

end end end end end
end

endmodule

ads-ee · Oct 7, 2014

I'm not going to review everything, this code doesn't look like any up front design was done. I'll just point out something that is blatantly wrong.

Code:

  if (count < 10000000)   // 10000000 COUNTS FROM ONBOARD 20 MHZ CLOCK
   begin
	  count <= count + 1;
	  led <= 1'b0;	       // UPTO 0.5 SEC THE LED WILL BE LOW
	end
 else
  begin
   if (count < 20000000)   // FOR 1HZ
	 begin
	   count <= count + 1;
		led <= ~led;		// LED WILL BE HIGH UPTO 1 SEC 
	 end

count < 10000000 will count from 0-10000000 = 10000001 counts which is fractionally more than 0.5 sec.
count < 20000000 will count from 0-20000000 = 20000001 counts which is fractionally more than 1 sec.
led <= ~led; will result in the led signal toggling like a clock until [count] reaches 20000000. Given the miscounting I think it may even stop toggling when led == 1.

Generating all the 7-seg outputs using combinational logic can result in glitches on the output, you probably won't be able to see them as LEDs don't vissibly respond to ns transitions.

As a design exercise: How does time count? in seconds 0-59, when 59 seconds...in minutes 0-59, when 59 minutes...in hours 0-23 so if we BCD encode the time:

Code:

reg [3:0] sec [0:1]; // [0] - seconds (0-9), [1] - 10's of seconds (0-5)
reg [3:0] min [0:1]; // [0] - minutes (0-9), [1] - 10's of minutes (0-5)

//....synchronous code that occurs every second
  // count seconds, @1sec
  sec[0] <= (sec[0] < 9) ? sec[0] + 1 : 0;

  // count 10's of seconds, @9sec
  if (sec[0] == 9)
    sec[1] <= (sec[1] < 5) ? sec[1] + 1 : 0;

  // count minutes, @59sec
  if (sec[1] == 5 && sec[0] == 9)
    min[0] <= (min[0] < 9) ? min[0] + 1 : 0;

  // count 10's of minutes, @ 9min, 59sec
  if (min[0] == 9 && sec[1] == 5 && sec[0] == 9)
    min[1] <= (min[1] < 5) ? min[1] + 1 : 0;

You could then create a function that converts BCD to 7-seg and use that function to convert the BCD digits in a clocked process into your outputs.

Regards

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Real time clock in verilog

santh92

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